Sony MDX-61 Service Manual ▷ View online
– 31 –
– 32 –
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
21
22
23
24
25
26
A0–A9
SENSE REFRESH AMP
INPUT/OUTPUT CONTROL SWITCH
(4) INPUT
BUFFER
(4) OUTPUT
BUFFER
CLOCK OSC
COLUMN DECODER
MEMORY CELL
(4194204 BIT)
A0–A9
ROW DECODER
GND
D4
D3
XCAS
XOE
NC
NC
NC
A8
A7
A6
A5
A4
VDD
A3
A2
A1
A0
A9
NC
NC
NC
XRAS
XWE
D2
D1
ADDRESS BUFFER
IC550
CS4330-KSR-H
IC700, 701
LB1638M
DE-EMPHASIS
VOLTAGE REFERENCE
INTERPOLATOR
DELTA-SIGMA
MODULATOR
ANALOG
LOW-PASS
FILTER
DAC
SERIAL INPUT
INTERFACE
1
2
3
4
5
6
7
8
SDATAI
DEM/SCLK
LRCK
MCLK
AOUT L
VA+
AGND
AOUT R
1
2
3
4
5
6
7
8
9
10
GND
IN1
VCC
IN2
GND
N.C.
OUT2
VS
OUT1
N.C.
CONTROL LOGIC
– POWER section –
IC900
MM1284XFFE
IC950
TL1451ACDB-E20
RESET
SW
SW
SW
1
2
3
4
5
6
7
8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DATA OUT
DATA IN
RESET
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON INPUT
BUS ON OUT
REFERENCE
VOLTAGE
LATCH
TRIANGLE
OSCILLATOR
VERF.
+2.5V
+2.5V
+2.5V
+
–
U.V.L.O
–
+
+
+
–
–
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
PWM
COMPA-
RATOR2
RATOR2
OUTPUT2
OUTPUT1
GND
PWM
COMPA-
RATOR1
RATOR1
VERF
S
R
R
VERF
VERF
ERROR
AMP2
ERROR
AMP1
VREF/2
SHORT
CIRCUIT
PROTECTION
COMPARATOR
VCC
+
REF
OUT
S.C.P
NON-INV-
INPUT2
INV-
INPUT2
FEED
BACK2
DEAD
TIME
CONTROL2
OUT2
VCC
GND
OUT1
RT
NON-INV-
INPUT1
INV-
INPUT1
FEED
BACK1
DEAD
TIME
CONTROL1
CT
•
IC Block Diagrams
– SERVO section –
– MAIN section –
IC501
HM51W4400TT6-8
IC200
CXD2535CR-1
SHCK
4
DFCT
3
FOK
2
TEOK
1
75
70
69 68 67 66 65
63 62 61 60
59
58
57
56 55
54
53 52 51
50 DVSS
DIPO
TEST2
MVC1
RAOF
EFMO
49
48
46
45
GFS
43
GTOP
42
RFCK
40
WDCK
39
DVDD
38
XBCK
37
MCLK
36
XTAI
35
XTAO
34
LRCK
33
BCK
32
C2PO
31
DTO
30
DTI
DIDT
28
DODT
27
DOVF
26
WFCK
41
XPLCK
44
74
73
72
71
AVSS
ADRB
ADRT
AVDD
BIA2
ADIO
VC
AUX
FE
ABCD
BOTM
PEAK
FILO
FILI
PCO
CLTV
AVSS
DVDD
DIFO
DIFI
DICV
RFI
BIAS
ASYI
ASYO
DVSS
25
REC
ADER
23
FMCK
22
DOUT
20
SBIOT
SBODT
18
SBOCK
XRST
DQSY
15
SQSY
14
ADSY
13
SENS
12
SRDT
11
XLAT
10
SCLK
9
SWDT
8
DIRC
7
WRPWR
SSTOP
DVSS 100
COUT 99
OFTRK 98
XDCL 97
DCLI 96
DCLO 95
SPFD 94
SPRD 93
SFDR 92
SRDR 91
FS4 90
FRDR 89
DVDD 88
FFDR 87
TFDR 86
TRDR 85
LDDR 84
TS25 83
ADFG
TEST1 81
APC 80
MID 79
TENV 78
TE 77
SE 76
DIN
ANALOG MUX
34 MHz
PLL
A/D
CONVERTER
OP AMP
SERVO DSP
PWM GENERATOR
DIGITAL
CLV
PROCESSOR
OFTRK/DFCT/
FOK/C OUT/
SHCK/TEOK
SHCK/TEOK
PROCESSOR
SERVO
CONTROL
CPU I/F
SENS
CONTROL
SERVO AUTO
SEQUENCER
APC COMP./
FILTER
APC PWM
GENERATOR
DIN PLL
(22 MHz)
COMP
ECC
ENCODER/
DECODER
REGISTER
32K RAM
REGISTER
AUDIO
DATA
CONTROL
EFM
MODULATOR
TIMING
GENERATOR
EFM
DIGITAL PLL
EFM SYNC
DETECTOR/
PROTECTOR
TIMING GENERATOR
DIGITAL
AUDIO
IN/OUT
PEAK
DETECT
64
47
EFM
DEMODULATOR
CLOCK
GENERATOR
29
24
21
19
SUBCODE
P~W
PROCESSOR
17
16
ADIP
DEMODULATOR
ADIP
DECODER
6
5
82
TRACKING PWM
FOCUS PWM
SLED PWM
TRACKING SERVO
FOCUS SERVO
SLED SERVO
SUBCODE Q
READER/
GENERATOR
VC
VC
VC
VC
VC
VC
VC
VC
36
7
VG
VD
12
VD
16
VD
8
FO1
11
RO1
9
PGND
10
PGND
15
FO2
13
RO2
14
PGND
21
VD
25
VD
30
VD
29
FO3
26
RO3
27
PGND
28
PGND
22
FO4
24
RO4
23
PGND
2
VC
3
CLK
34
PS
6
FI1
5
RI1
33
OE
17
FI2
18
RI2
31
FI3
32
RI3
20
F/R4
19
PI4
4
GND
35
GND
1
G
VC
VC
CLOCK
DC/DC
CONVERTER
CLK
DETECTOR
DRIVER
PRE-DRIVER
CONTROL
DRIVER
PRE-DRIVER
CONTROL
DRIVER
PRE-DRIVER
CONTROL
DRIVER
PRE-DRIVER
CONTROL
IC300
MPC17A38ZVMEL
– 33 –
Pin No.
Pin Name
I/O
Function
3-8.
IC PIN FUNCTION DESCRIPTION
SERVO BOARD IC100 CXA1981AR (RF AMP)
1
VC
O
Output terminal for the center point voltage (1/2 VCC) generated
2-7
A-F
I
Signal input from detector circuit in the optical pick-up block
8
FI
I
Signal input of the operational amplifier for F signal
9
FO
O
Signal output of the operational amplifier for F signal
10
PD
I
Front monitor Connected to the photo diode
11
APCREF
I
Input terminal for the setting of laser power
12
TEMPI
I
Terminal for the connection to temperature sensor Not used this set (OPEN)
13
GND
–
Ground terminal
14
AAPC
O
LD amplifier output terminal of APC circuit
15
DAPC
O
Not used (OPEN)
16
TEMPR
O
Output terminal of the reference voltage for temperature sensor Not used this set (OPEN)
17
XRST
I
Reset signal input from the system controller (IC600) When reset : “L”
18
SWDT
I
Write data signal input from the system controller (IC600)
19
SCLK
I
Clock signal input from the system controller (IC600)
20
XLAT
I
Latch signal input from the system controller (IC600)
21
VREF
O
Reference voltage output Not used this set (OPEN)
22
TENV
O
Not used (OPEN)
23
THLD
I
Not used (OPEN)
24
VCC
–
Power supply terminal (+3.3V)
25
TFIL
I
Not used (OPEN)
26
TE
O
Tracking error signal output to CXD2535CR (IC200)
27
TLB
I
Input terminal of the adder signal to tracking error
Not used this set (OPEN)
28
CSLED
I
Terminal for the sled error lowpass filter
29
SE
O
Sled error signal output to CXD2535CR (IC200)
30
ADFM
O
FM signal output terminal of the ADIP
31
ADIN
I
Input terminal by AC coupling is FM signal of the ADIP
32
ADAGC
I
External capacitor connect terminal for AGC of the ADIP
33
ADFG
O
ADIP double turned FM signal output to CXD2535CR (IC200) (22.05kHz
±
1kHz)
34
AUX
O
Sub signal output to CXD2535CR (IC200)
35
FE
O
Focus error signal output to CXD2535CR (IC200)
36
FLB
I
Input terminal of the adder signal to focus error
Not used this set (OPEN)
37
ABCD
O
Light amount signal output to CXD2535CR (IC200)
38
BOTM
O
Light amount bottom hold signal output to CXD2535CR (IC200)
39
PEAK
O
Light amount peak hold signal output to CXD2535CR (IC200)
40
PFAGC
I
External capacitor connect terminal of AGC circuit for the RF
41
RF
O
Playback EFM RF signal output to CXD2535CR (IC200)
42
ISET
I
Setting terminal for the internal circuit constant
22kHz, BPF center frequency
43
AGCI
I
Input terminal by AC coupling is RF signal
44
RFO
O
RF signal output terminal
45
MORFI
I
Input terminal by AC coupling is RF signal of the MO
46
MORFO
O
RF signal output terminal of the MO
47, 48
I, J
I
Signal input from detector circuit in the optical pick-up block
– 34 –
Pin No.
Pin Name
I/O
Function
1
FS256
O
11.2896MHz clock signal output (MCLK system) Not used this set (OPEN)
2
FOK
O
Focus OK signal output to the system controller (IC600) “H” is output when the focus is applied
3
DFCT
O
Defect ON/OFF selection signal output to CXD2536CR (IC500)
4
SHCK
O
Track jump detection signal output to the system controller Not used this set (OPEN)
5
SHCKEN
I
Track jump detection enable input Not used this set (Fixed at “L”)
6
WRPWR
I
Laser power selection signal input from the system controller Not used this set (Fixed at “L”)
7
DIRC
I
Not used this set (Fixed at “H”)
8
SWDT
I
Write data signal input from the system controller (IC600)
9
SCLK
I
Serial clock signal input from the system controller (IC600)
10
XLAT
I
Serial latch signal input from the system controller (IC600)
11
SRDT
O
Read data signal output to the system controller (IC600)
12
SENS
O (3)
Internal status (SENS) output to the system controller (IC600)
13
ADSY
O
ADIP sync signal output Not used this set (OPEN)
14
SQSY
O
Sub-code Q sync (SCOR) output to the system controller (IC600)
“L” every 13.3msec, Almost “H”
15
DQSY
O
Digital in U-bit CD format sub-code Q sync (SCOR) output to the system controller (IC600)
“L” every 13.3msec, Almost “H”
16
XRST
I
Reset sigmal input from the system controller (IC600) When reset “L”
17
TEST4
I
Test input terminal (Fixed at “L”)
18
CLVSCK
O
Not used this set (OPEN)
19
TEST5
I
Test input terminal (Fixed at “L”)
20
DOUT
O
Output terminal of the digital audio signal (for optical out) Not used this set (OPEN)
21
DIN
I
Input terminal of the digital audio signal (for optical out)
Not used this set (Fixed at “L”)
22
FMCK
O
FM modulation clock signal output of the ADIP Not used this set (OPEN)
23
ATER
O
ADIP CRC flag output When error “H” Not used this set (OPEN)
24
REC
I
Record/playback selection signal input
When recording :“H”, when playback :“L” (Fixed at “L”)
25
DVSS
–
Ground terminal (Digital system)
26
DOVF
I
Validity flag input terminal for the digital audio out Not used this set (Fixed at “L”)
27
DODT
I
Input terminal of 16-bit data signal for the digital audio out Not used this set (Fixed at “L”)
28
DIDT
O
Output terminal of 16-bit data signal for the digital audio in Not used this set (OPEN)
29
DTI
I
Record audio data signal input from CXD2536CR (IC500)
30
DTO
O (3)
Plyback audio data signal output to CXD2536CR (IC500)
31
C2PO
O
C2PO (indicate the error state of the data) signal output to CXD2536AR (IC500)
Playback : C2PO (“H”), Digital recording : D. In-Vflag, Analog recording : “L”
32
BCK
O
Bit clock (2.8224MHz) signal output to CXD2536CR (IC500) (MCLK system)
33
LRCK
O
L/R clock (44.1kHz) signal output to CXD2536CR (IC500) (MCLK system)
34
XTAO
O
System clock (512Fs=22.5792MHz) signal output Not used this set (OPEN)
35
XTAI
I
System clock (512Fs=22.5792MHz) signal input from CXD2536CR (IC500)
36
MCLK
O
MCLK clock (22.5792MHz) signal output Not used this set (OPEN)
37
XBCK
O
BCK (pin #™) inverted output Not used this set (OPEN)
38
DVDDO
–
Power supply terminal (+3.3V) (Digital system)
39
WDCK
O
WDCK clock (88.2kHz) signal output (MCLK system) Not used this set (OPEN)
40
RFCK
O
RFCK clock (7.35kHz) signal output (MCLK system) Not used this set (OPEN)
SERVO BOARD IC200 CDX2535CR-1 (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC
ENCODER/DECODER)
ENCODER/DECODER)
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