Sony CDX-R3300EE Service Manual ▷ View online
13
CDX-R3300EE
2-10. SERVO BOARD
3
CN1
5
claw
6
SERVO board
4
toothed lock screw
(M 1.7)
1
Remove the eight solderings.
2
Remove the three solderings.
14
CDX-R3300EE
SECTION 3
DIAGRAMS
3-1. IC PIN DESCRIPTIONS
• IC3 CXD3059AR (DIGITAL SERVO/DIGITAL SIGNAL PROCESSOR) (SERVO BOARD (1/2))
Pin No.
Pin Name
I/O
Pin Description
1
MIRR
I/O
Mirror signal input/output (Not used in this set)
2
DFCT
I/O
Defect signal input/output (Not used in this set)
3
FOK
I/O
Focus OK signal input/output
4
VSS
—
Ground
5
LOCK
I/O
Lock signal input/output (Not used in this set)
6
MDP
O
Spindle motor servo control signal output
7
SSTP
I
Disc most inner detection signal input (Fixed at L in this set)
8
IOVSS1
—
Digital ground
9
SFDR
O
Sled drive signal output (FWD direction)
10
SRDR
O
Sled drive signal output (REV direction)
11
TFDR
O
Tracking drive signal output (FWD direction)
12
TRDR
O
Tracking drive signal output (REV direction)
13
FFDR
O
Focus drive signal output (FWD direction)
14
FRDR
O
Focus drive signal output (REV direction)
15
IOVDD1
—
Digital power supply pin (+3.3 V)
16
AVDD0
—
Analog power supply pin (+3.2 V)
17
AVSS0
—
Analog ground
18
NC
—
Not used. (Open)
19
E
I
E signal input
20
F
I
F signal input
21
TEI
I
Tracking error signal input
22
TEO
O
Tracking error signal output
23
FEI
I
Focus error signal input
24
FEO
O
Focus error signal output
25
VC
I/O
VC voltage output/Center voltage input
26
A
I
A signal input
27
B
I
B signal input
28
C
I
C signal input
29
D
I
D signal input
30
NC
—
Not used. (Open)
31
AVDD4
—
Analog power supply pin (+3.2 V)
32
RFDCO
I/O
RFDC signal input/output (Not used in this set)
33
PDSENS
I
Reference voltage input (Fixed at L in this set)
34
AC_SUM
O
RFAC summing amplifier signal output
35
EQ_IN
I
Equalizer circuit signal input
36
LD
O
APC amplifier signal output
37
PD
I
APC amplifier signal input
38
NC
—
Not used. (Open)
39
RFC
I
EQ cut off frequency adjustment input
40
AVSS4
—
Analog ground
41
RFACO
O
RFAC signal output
42
RFACI
I
RFAC signal input
43
AVDD3
—
Analog power supply pin (+3.2 V)
44
BIAS
I
Asymmetry circuit constant current input
45
ASYI
I
Asymmetry comparate voltage input
46
ASYO
O
EFM full swing signal output
47
VPCO
O
Charge pump output
48
VCTL
I
VCO2 control voltage input
49
AVSS3
—
Analog ground
50
CLTV
I
VCO1 control voltage input
51
FILO
O
Filter signal output
15
CDX-R3300EE
Pin No.
Pin Name
I/O
Pin Description
52
FILI
I
Filter signal input
53
PCO
O
Charge pump output
54
AVDD5
—
Analog power supply pin (+3.3 V)
55
DDVROUT
O
DC/DC converter output
56
DDVRSEN
I
DC/DC converter output voltage monitor signal input
57
AVSS5
—
Analog ground
58
DDCR
I
Reset signal input
59
NC
—
Not used. (Open)
60
BCKI
I
D/A interface bit clock signal input
61
PCMDI
I
D/A interface serial data signal input
62
LRCKI
I
D/A interface LR clock signal input
63
LRCK
O
D/A interface LR clock signal output
64
VSS
—
Ground
65
PCMD
O
D/A interface serial data signal output
66
BCK
O
D/A interface bit clock signal output
67
VDD
—
Power supply pin (+2.6 V)
68
EMPH
O
Not used. (Open)
69
EMPHI
I
Not used. (Fixed at L in this set)
70
IOVDD2
—
Digital power supply pin (+3.3 V)
71
DOUT
—
Digital out signal output (Not used in this set)
72, 73
TEST
I
Test pin (Normally, fixed at L)
74
IOVSS2
—
Digital ground
75
NC
—
Not used. (Open)
76
XVSS
—
Ground
77
XTAO
O
Master clock signal output (16.9344 MHz)
78
XTAI
I
Master clock signal input (16.9344 MHz)
79
XVDD
—
Power supply pin (+2.6 V)
80
AVDD1
—
Analog power supply pin (+3.3 V)
81
AOUT1
O
L channel analog signal output
82
VREFL
O
L channel reference voltage output
83, 84
AVSS1,AVSS2
—
Analog ground
85
VREFR
O
R channel reference voltage output
86
AOUT2
O
R channel analog signal output
87
AVDD2
—
Analog power supply pin (+3.3 V)
88
NC
—
Not used. (Open)
89
IOVDD0
—
Digital power supply pin (+3.3 V)
90
RMUT
O
R channel “0” detection flug output
91
LMUT
O
L channel “0” detection flug output
92
NC
—
Not used. (Open)
93
XTSL
I
Sub clock signal input (Fixed at L in this set)
94
IOVSS0
—
Digital ground
95
XTACN
I
Oscillation circuit control signal input (Fixed at H in this set)
96
SQSO
O
Sub 80 bit, PCM peak and level data signal output
97
SQCK
I
Clock signal input
98
SBSO
O
Sub P-W serial data signal output (Not used in this set)
99
EXCK
I
Clock signal input (Not used in this set)
100
XRST
I
System reset signal input
101
SYSM
I
Mute signal input (Fixed at L in this set)
102
DATA
I
Serial data signal input
103
VSS
—
Ground
104
XLAT
I
Latch signal input
105
CLOK
I
Serial data transfer clock signal input
106
VDD
—
Power supply pin (+2.6 V)
16
CDX-R3300EE
Pin No.
Pin Name
I/O
Pin Description
107
SENS
O
SENS signal output
108
SCLK
I
Clock signal input
109
ATSK
I/O
Input/output for anti-shock. (Fixed at L in this set)
110
WFCK
O
WFCK signal output (Not used in this set)
111
XUGF
O
XUGF signal output (Not used in this set)
112
XPCK
O
XPCK signal output (Not used in this set)
113
GFS
O
GFS signal output
114
C2PO
O
C2PO signal output
115
SCOR
O
Sub code sync signal output
116
VDD
—
Power supply pin (+2.6 V)
117
C4M
O
4.2366 MHz signal output (Not used in this set)
118
WDCK
O
Word clock signal output (Not used in this set)
119
COUT
I/O
Track count signal output/output (Not used in this set)
120
NC
—
Not used. (Open)
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