Sony CDX-GT500 / CDX-GT500EE / CDX-GT50W / CDX-GT550 Service Manual ▷ View online
33
CDX-GT50W/GT500/GT500EE/GT550
• IC Block Diagrams
IC1 BA5968FP-E2 (SERVO Board (2/2))
1
2
11
13
14
12
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
MUTE
FWD
FWD
LDCTL
NC
OPOUT1
NC
NC
OPOUT2
POWVCC
VCC
VOL–
VOL+
VOL2–
VOL2+
VO1–
VO1+
REV
OPIN4+
OPIN4–
OPOUT4
OPIN3+
OPIN3–
OPOUT3
MUTE
VOL+
GND
VOL3–
VOL3+
VOL4–
VOL4+
REV
OUTR OUTF
10
9
8
7
6
5
28
27
26
25
24
23
22
21
20
19
18
17
16
15
4
3
IC350 TDA7333013TR (MAIN Board (1/3))
VDDA
INTERPOLATOR
RAM
BUFFER
&
CONTROL
LOGIC
TEST LOGIC
&
PIN MUX'S
I
2
C/SPI
INTERFACE
BAND PASS
FILTER
SIGMA DELTA
CONVERTER
SINC4
FILTER
REF3
REF2
REF1
VSS
VDDD
RESETN
TM
1
MPX
16
CSN
SDAOUT
RDSREG
3
INTN
MPX
SINC4REG
SDAIN
SCK
SPI
TESTREG
SCK
SPI
TESTREG
14
2
3
4
5
6
7
8
INTN
15
SA_DATAOUT
13
SDA_DATAIN
12
SCL_CLK
11
OSCILLATOR
XTO
10
XTI
9
RDS
DEMODULATOR &
SYNCHRONIZATION
2
34
CDX-GT50W/GT500/GT500EE/GT550
IC150 TDA8588AJ/N2/R1 (MAIN Board (1/3))
MUTE
MUTE
ENABLE
LOGIC
STANDBY
MUTE
CHIP DETECT
DIAGNOSTIC
PROTECTION
DIAGNOSTIC
SWITCH
REGULATOR
SWITCH
REFERENCE
VOLTAGE
LOADDUMP
PROTECTION
TEMPERATURE
PROTECTION
BACK-UP
SWITCH
REGULATOR
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
TAB
OUT FL-
OUT FL+
OUT RL-
OUT RL+
INRL
SGND
INRR
OUT RR+
OUT RR-
OUT FR+
OUT FR-
DIAG
SW2(ANT REM)
SW1(ANT REM)
REG3(SERVO)
REG4(DR+B)
VP(REG)
REG2(BU 5V)
SDA
SCL
VP2
PGND3
SVR
INFL
INFR
AC GND
PGND2
VP1
STB
PGND1
RST
CRES
REG1(AUDIO +B)
GND(REG)
REG5(ILL)
CBU
FL
RL
RR
VP
FR
I2C BUS
IC450 BA8271F-E2 (MAIN Board (2/3))
1
2
3
4
5
5
6
7
8
9
10
14
13
12
11
BUS ON
SWITCH
RESET
SWITCH
BATTERY
SWITCH
BUS ON
RST
BATT
CLK
VREF
GND
VCC
RESET
BUS ON
BUS ON
CLK IN
BU IN
DATA IN
DATA OUT
DATA
35
CDX-GT50W/GT500/GT500EE/GT550
IC401 TDA7419TR (MAIN Board (1/3))
2
3
1
4
5
6
7
SUPPLY
I2C BUS
DIGITAL CONTROL
INPUT
MULTIPLEXER
15
18
17
16
16
19
20
21
22
23
24
27
25
26
28
8
9
10
11
12
13
14
SOFTSEP
MONO FADER
SOFTSEP
MONO FADER
SOFTSEP
MONO FADER
SUBWOOFER
L.P.F
MIX
MIX
HPF
BUSS
MIDDLE
SPECTRUM
ANALYZER
TREBLE
SOFTSTEP
VOLUME
IN GAIN
AUTO ZERO
SOFT
MUTE
LOUDNESS
HPF
SOFTSEP
MONO FADER
SOFTSEP
MONO FADER
SOFTSEP
MONO FADER
ACOUTR
ACINR
ACINL
ACOUTL
AC2INL
AC2INR
SE2L
SE2R
SE1L
SE1R
DIFFL
DIFFG
DIFFR
CREF
GND
OUTLR2
OUTRF
OUTRR1
OUTLR1
OUTLF
MUTE
SCL
SDA
VDD
SAIN
SAOUT
VREF
OUTRR2
36
CDX-GT50W/GT500/GT500EE/GT550
• IC Pin Descriptions
IC3 MB90486BPFV-G-177E1 (CD SYSTEM CONTROL) (SERVO BOARD (2/2))
Pin No.
Pin Name
I/O
Pin Description
1
CDON 1500MV
O
Servo 1.5 V power supply control signal output
2 to 5
NC
—
Not used. (Open)
6
DRVON
O
Motor drive on/off control signal output
7
CD BUS0
I/O
Bus data signal input/output 0
8
CD BUS1
I/O
Bus data signal input/output 1
9
VSS
—
Ground pin
10
CD BUS2
I/O
Bus data signal input/output 2
11
CD BUS3
I/O
Bus data signal input/output 3
12
CD BUCK
O
Bus clock signal output
13
CD XCCE
O
Chip enable signal output
14
CD XRST
O
Reset signal output
15
CD ZDET
I
Zero detection signal input
16 to 20
NC
—
Not used. (Open)
21
VCC
—
Power supply pin (+3.3 V)
22
DAC ZDETL
I
Zero data detection signal input (L-ch)
23
DAC ZDETR
I
Zero data detection signal input (R-ch)
24
NC
—
Not used. (Open)
25
RXD
I
UART RXD data signal input (MCBUS/Flash data input)
26
TXD
O
UART TXD data signal output (MCBUS/Flash data output)
27
DEC SSTBY
O
SRAM STANDBY mode control signal output
28, 29
NC
—
Not used. (Open)
30
DEC INT
I
Request signal input
31, 32
NC
—
Not used. (Open)
33
AVCC
—
Power supply pin (+3.3 V) for A/D converter
34
AVRH
—
External reference voltage for A/D converter
35
AVSS
—
Ground pin
36
NC
—
Not used. (Open)
37
DEC XMUTE
O
Mute signal output L: mute
38, 39
NC
—
Not used. (Open)
40
VSS
—
Ground pin
41
NC
—
Not used. (Open)
42
MEC LIMIT
I
Sled limit in detection switch signal input
43
MEC LOAD
O
Loading motor signal output (Load direction)
44
MEC EJECT
O
Loading motor signal output (Eject direction)
45
MEC INSW
I
Pack-in detection signal input
46
MEC DSW
I
Chucking end detection switch signal input
47, 48
MD0, MD1
I
CPU operation mode designation signal input (Connect to Vcc.)
49
MD2
I
CPU operation mode designation signal input (Connect to Vss.)
50
BUS ON
I
Bus on signal input L: bus on
51
BU IN
I
Backup on/off signal input H: backup on, L: backup off
52
NC
—
Not used. (Open)
53
MEC SELFSW
I
Disc insert detection switch signal input L: disc in interruption
54, 55
NC
—
Not used. (Open)
56
UNISI
I
Serial data signal input
57
UNISO
O
Serial data signal output
58
UNICKI
I
Serial clock signal input
59
LINKOFF
O
Line off signal output
60
A ATT
O
Audio attenuation signal output H: ATT on
61
EJECT OK
I
Front panel open signal input H: eject
62
OPEN REQ
O
Front panel open/close request signal output H: open request
63
MECON
O
Mechanism deck power supply control signal output
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