Sony CDX-F7000 / CDX-F7005X / CDX-FW700 Service Manual ▷ View online
17
CDX-F7000/F7005X/FW700
Pin No.
Pin Name
I/O
Pin Description
53
CD LM EJECT
O
CD eject signal output
54
CD RESET
O
CD reset signal output
55
CD AO
O
CD AO signal output
56
CD STB
O
CD strobe signal output
57
(NCO)
O
Not used
58
CD RF OK
I
CD RF OK signal input
59
CD ON
I
CD ON signal input
60
VCC2
—
Power supply pin (+5V)
61
DISP RESET
O
Display CPU reset signal output
62
VSS
—
Ground
63
TEST IN
I
Test mode signal input
64
BUS ON
O
BUS ON signal output
65
SYS RST
O
System reset signal output
66
BUS/AUX
O
BUS AUDIO/AUX-IN select signal output
67
(NCO)
O
Not used
68
ACC IN
I
ACC power supply check signal input
69
ILL IN
I
ILL check signal input
70
RC IN1
I
Rotary commander signal input
71
CDM ON
I
CD power supply ON signal input
72
CD SELF SW
I
CD SELF switch detection signal input
73
TU ATT IN
I
Tuner attenuator zero cross signal input
74
ZERO DET1
I
ZERO detection signal input 1
75
ZERO DET2
I
ZERO detection signal input 2
76
Z ATT
I
Z mute signal input
77
(NCO)
O
Not used
78
(NCO)
O
Not used
79
ROMC EN
O
Connecting to ground.
80
QUALITY
I
Tuner noise detection signal input
81
MPTH
O
Not used
82
VSM
I
S-meter signal input
83
SA IN
I
Spectrum analyzer data input
84
KEY IN1
I
Key signal input
85
KEY IN0
I
Key signal input
86
RC IN0
I
Rotary commander signal input
87
KEY ACK2
I
Rotary commander ACK signal input
88
KEY ACK0
I
Key ACK signal input
89
KEY ACK1
I
Key ACK signal input
90
DOORING
O
Sub panel LED power supply control signal output
91
RAM BU
I
RAM back-up input
92
FLD ON
O
FL driver power supply control signal output
93
FL ON
O
FL power supply control signal output
94
AVSS
—
Ground
95
DISP CE
O
Display CPU chip enable output
96
VREF
—
AD converter reference voltage (+5V)
97
AVCC
—
Power supply pin (+5V)
98
DISP SI/RX
I
Display CPU serial data input
99
DISP SO/TX
O
Display CPU serial data output
100
DISP CKO
O
Display CPU serial clock output
18
CDX-F7000/F7005X/FW700
• IC901 M30823MH-080GP (DISPLAY CONTROL) (KEY BOARD)
Pin No.
Pin Name
I/O
Pin Description
1
SYS CE
I
Main chip enable input
2
(NCO)
O
Not used
3
FL DAT3
O
FL serial data output 3
4
(NCO)
O
Not used
5
FL CLK IN
I
FL serial clock input
6
BYTE
I
Connecting to ground.
7
CNVSS
I
Flash write-in signal input
8
PLL LPF
O
PLL low pass filter connection pin
9
PLL GND
I
Ground
10
RESET
I
CPU reset input
11
XOUT
O
Main clock signal output (8MHz)
12
VSS
—
Ground
13
XIN
I
Main clock signal input (8MHz)
14
VCC
—
Power supply pin (+5V)
15
NMI
I
Non maskable interrupt signal input
16
(NCO)
O
Not used
17
GCP IN
I
GCP pulse interrupt signal input
18, 19
(NCO)
O
Not used
20
GCP OUT
O
GCP pulse signal output
21
LAT
O
FL data LAT output
22
BK
O
FL BK signal output
23
GCP2
O
FL GCP signal output 2
24
(NCO)
O
Not used
25
GCP1
O
FL GCP signal output 1
26
(NCO)
O
Not used
27
GCP4
O
FL GCP signal output 4
28
GCP3
O
FL GCP signal output 3
29
SYS SO
O
Main bus serial data output
30
SYS SI
I
Main bus serial data input
31
SYS CLK
O
Main bus serial clock output
32
(NCO)
O
Not used
33
FL DAT1
O
FL serial data output 1
34
(NCO)
O
Not used
35
FL CLK
O
FL serial clock output
36 to 38
(NCO)
O
Not used
39
HOLD
I
External bus data input (HOLD)
40 to 43
(NCO)
O
Not used
44
WRI/WR
I
External bus data input (WRI/WR)
45 to 59
(NCO)
O
Not used
60
VCC
—
Power supply pin (+5V)
61
(NCO)
O
Not used
62
VSS
—
Ground
63 to 93
(NCO)
O
Not used
94
AVSS
—
Ground
95
(NCO)
O
Not used
96
VREF
—
Reference voltage (+5V)
97
AVCC
—
Power supply pin (+5V)
98
(NCO)
—
Not used
99
FL DAT2
O
FL serial data output 2
100
FL CLK IN
I
FL serial clock input
19
19
CDX-F7000/F7005X/FW700
82
83
84
85
20
16
D/A
CONV
TRACKING
ERROR
FORCUS
ERROR
1
OSC
EFM
DEMOD
SERVO
CTL
RF
EQ
EQ
13
12
11
10
9
8
6
47
72
45
46
3
4
5
56
55
54
58
I/F
87
86
2
1
LD
DRIVE
Q1
FOCUS
COIL
DRIVE
TRACKING
COIL
DRIVE
SLED
MOTOR
DRIVE
SPINDLE
MOTOR
DRIVE
LOADING
MOTOR
DRIVE
28
12
11
13
14
15
16
17
18
9
10
5
53
52
M902
(SLED)
M901
(SPINDLE)
M903
(LOADING)
SW4
(LIMIT)
SW2
(SELF)
SW1
(DOWN)
SW3
(DISC IN)
X1
16.9344MHz
OPTICAL PICK-UP
(KSS1000E)
I-V
CONV.
CDL
R-CH
CD_STB
CD_A0
CD_SO
CD_SI
CD_CKO
CD RESET
30
74 ZERO DET1
29
75 ZERO DET2
CD_RFOK
CD_INSW
CD_LIMIT
CD_SELFSW
CD_DSW
CD_LM_LOAD
CD_LM_EJECT
TUNER
SECTION
A
23
24
M
M
M
LOUT
ROUT
SI
7
16 CD_INTQ
INTQ
RFOK
LMUTE
RMUTE
SO
SCK
STB
A0
RST
PD
LD
A
C
B
D
E
F
PD
LD
LD AMP
FOCUS
COIL
TRACKING
COIL
FD+
FD+
FD-
TD+
TD-
SD+
SD-
MD+
MD-
FSC+
FSC-
TRK+
TRK-
SL-
SL+
SP-
SP+
LD-
LD+
LOAD
EJECT
SYSTEM CONTROL
IC303 (1/3)
RF AMP,DIGITAL SERVO,
DIGITAL SIGNAL PROCESSOR
IC1
FOCUS/TRACKING COIL DRIVE,
SLED/SPINDLE/LOADING MOTOR DRIVE
IC2
6
FD-
2
TD+
3
TD-
27
SD+
26
SD-
24
MD+
23
MD-
Signal path
: CD
A3.3V
AU3.3V
D3.3V
DR6V
CD+3.3V
CD+6V
+
-
+
-
+
-
52 53 54 55 56 57 58 59
IC251 (1/3) 6
2
IC251 (2/3)
1
7
IC251 (3/3)
3
5
R-CH is omitted due to same as L-CH
3-2. BLOCK DIAGRAM — CD SECTION —
(Page 20)
20
20
CDX-F7000/F7005X/FW700
1 ANT
40 TUNER LCH
ELECTRONIC VOLUME
IC401
J601
(ANTENNA)
TUX501
(TUNER UNIT)
CONTROLLED POWER AMP/
MULTIPLE VOLTAGE REGULATOR
IC201
SYSTEM CONTROL
IC303 (2/3)
CNP101
41 TUNER RCH
BATT
42 CD LCH
43 CD RCH
R-CH
4
3
3
10
VCC
11
TU VDD
15
E2P VDD
13
TU-SCL
14
TU-SDA
6
S-METER
7
TU MUTE
16
E2P SCL
17
E2P SDA
82 VSM
8
MUTE CONDITION
73 TU ATTIN
AU+8V
TU+5V
BU+5V
BU+5V
32 TUNER ATT
34 EEP SCL
33 EEP SIO
33 EEP SIO
L
R
CD-L
R-CH
17
22
OUTSW
OUT RF
21
OUT RR
R-CH
L
R
5
3
3
FL+
FL-
9
7
7
RL+
RL-
29
27
27
SW1
R-CH
SW2
BATT
30
37
37
REG1
REG2
31
33
33
REG3
REG4
34
REG5
TU+5V
BATT
14
16
16
SA IN
SA OUT
15
MUTE
2 SDA
AU+8V
BU+5V
CD+3.3V
CD+6V
CD+6V
ILL+B
4 SCL
SDA
SCL
16 ACGND
22 STB
25 DIAG
25 DIAG
AU+8V
35 VP
15
13
7
10
12
11
16
1
9
2
4
3
5
6
13
12
12
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
27
IIC SCK
28
IIC SIO
26
VOL ATT
25
ATT
20
BEEP
41
AMP STB
40
AMP DIAG
83
SA IN
23
SA CLK
66
BUS/AUX
18
BU IN
63
TEST IN
12 INFL
FL+
FL-
RL+
RL-
FR+
FR-
RR+
RR-
AMP-REM
ANT-REM
ACC
TEST
25
OUT LF
11 INRL
24
OUT LR
MUTE
Q171
REAR
AUDIO OUT
MUTE CONTROL
Q401,402
30
UNI SI
29
UNI SO
31
UNI CKO
64
BUS ON
65
SYS RST
10 B CHK
8 DATA OUT
9 DATA IN
11 CLK IN
12 BUSON
13 RST
3
5
4
7
6
2
1
3
BATT
6
DATA I/O
4
CLK
1
BUS ON
2
RST
68
ACC IN
ACC CHECK
Q102
TU+5V REG
Q501
BATT
BATT
BATT DET
Q101
BUS INTERFACE
IC110
MUTE
Q181
ATT
24
TEL ATT
TEL ATT
Q103
14
69
ILL IN
ILL
D401
F901
R-CH
L
R
FRONT
AUDIO OUT
R-CH
4
7
7
PB LCH
PB RCH
R-CH
L
R
BUS
AUDIO IN
PJ401
CN401
SUB OUT(MONO)
BUS
CONTROL
IN
D105
CD
SECTION
A
TH100
CNP102
8
BATT
ILL CHECK
Q907
GROUND SW
Q408
MUTE
Q470
• Signal Path
• R-CH is omitted due to same as L-CH.
: CD PLAY
: FM
: AM
3-3. BLOCK DIAGRAM — MAIN SECTION —
(Page 19)
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