Sony CDX-F5500N Service Manual ▷ View online
17
CDX-F5500N
65
NCO (TUON)
O
Not used. (Open)
66
NSMASK
O
Noise mask output (Not used in this set)
67
E2P_CKO
O
Serial clock output to EEPROM communication.
68
E2P_SIO
I/O
Serial data input/output with EEPROM communication.
69
DOORIND
O
Door indicator detection output
70
AMPSTB
O
Standby control output to power amp IC.
71
NCO
O
Not used. (Open)
72
FLS.SO/LCDSO
O
Serial data output to LCD driver IC.
73
FLS.SI/LCDCE
O
Chip enable output to LCD driver IC.
74
LCDCKO
O
Serial clock output to LCD driver IC.
75 to 78
NCO
O
Not used. (Open)
79
I2C_SIO
I/O
I2C bus serial data input/output
80
NCO
O
Not used. (Open)
81
I2C_CKO
O
I2C bus serial clock output
82
DAVN
I
RDS data block synchronization detection input (Not used in this set)
83
SIRCS
I
SIRCS signal input
84
NCO
O
Not used. (Open)
85
BEEP
O
Beep output to power amp IC.
86 to 88
NCO
O
Not used. (Open)
89
VDD3
—
Power supply pin (+3.3 V)
90
NCO
O
Not used. (Open)
91
VSS3
—
Ground
92
QUALITY
I
Noise detection input (Not used in this set)
93
VSM
I
S-meter voltage detection input
94, 95
KEYIN1, 0
I
Key input 1, 0
96
RCIN0
I
Rotary commander key input
97 to 99
NCO
O
Not used. (Open)
100
VREF+
—
A/D converter power supply (+) pin (+3.3 V)
Pin No.
Pin Name
I/O
Pin Description
18
CDX-F5500N
• A : B+ Line.
• Power voltage is dc 14.4V and fed with regulated dc power
• Power voltage is dc 14.4V and fed with regulated dc power
supply from ACC and BATT cords.
• Voltages are taken with a VOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal production
tolerances.
tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal production
tolerances.
tolerances.
• Circled numbers refer to waveforms.
• Signal path.
F
: FM
f
: AM
J
: CD
for printed wiring boards:
• X : parts extracted from the component side.
• Y : parts extracted from the conductor side.
•
• X : parts extracted from the component side.
• Y : parts extracted from the conductor side.
•
a
: Through hole.
•
: Pattern from the side which enables seeing.
(The other layer’s patterns are not indicated.)
• Waveforms
— Servo Board —
(MODE: CD PLAY)
— Servo Board —
(MODE: CD PLAY)
THIS NOTE IS COMMON FOR PRINTED WIRING
BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is
printed in each block.)
BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is
printed in each block.)
for schematic diagram:
• All capacitors are in µF unless otherwise noted. (p: pF)
• All capacitors are in µF unless otherwise noted. (p: pF)
50 WV or less are not indicated except for electrolytics
and tantalums.
and tantalums.
• All resistors are in Ω and
1
/
4
W or less unless otherwise
specified.
•
%
: indicates tolerance.
•
f
: internal component.
• C : panel designation.
IC3
whwk
(A, C)
3
0V
Approx.
150mVp-p
150mVp-p
16.9344MHz
IC3
uj
(XTAO)
0V
2
Approx. 100mVp-p
IC3
wd
(FEI)
1
Approx. 100mVp-p
IC3
wa
(TEI)
IC3
wjwl
(B, D)
4
6
2Vp-p
IC3
ra
(RFACO)
5
18.43MHz
IC4
ia
(X1)
7
1Vp-p
Approx.
150mVp-p
150mVp-p
Approx.
0.8Vp-p
0.8Vp-p
32.768kHz
IC500
qh
(XOUT)
— Main Board —
2
27.648MHz
IC500
qs
(OSCOUT)
2.8Vp-p
2.6Vp-p
1
Caution:
Pattern face side: Parts on the pattern face side seen from the
(Side B)
Pattern face side: Parts on the pattern face side seen from the
(Side B)
pattern face are indicated.
Parts face side:
Parts on the parts face side seen from the
(Side A)
parts face are indicated.
Note: The components identified by mark 0 or dotted line
with mark 0 are critical for safety.
Replace only with part number specified.
Replace only with part number specified.
CDX-F5500N
19
19
CDX-F5500N
46
ASYO
RF AMP,DIGITAL SERVO,
DIGITAL SIGNAL PROCESSOR
IC3
41
RFACO
24
FEO
22
TEO
42 RFACI
23 FEI
21 TEI
13 FFDR
PD1
PD2
E
F
I-V AMP
PD
LD
DETECTOR
45 ASYI
27
26
29
28
19
20
E
C
D
A
B
F
36 LD
37
PD
(FOCUS)
(TRACKING)
2-AXIS DEVICE
OPTICAL
PICK-UP BLOCK
(KSS1000E)
• Signal path
: CD
LASER DIODE
M
M
M
13
12
VO1–
VO1+
6
7
VO4+
VO4–
8
9
VO3–
VO3+
5
4
VOL+
VOL–
FWD
REV
1
2
VIN2+ 22
14 FRDR
VIN2– 21
11 TFDR
VIN1+B 19
12 TRDR
VIN1–B 18
9 SFDR
VIN4+ 31
10 SRDR
VIN4– 32
6 MDP
VIN3+ 25
MUTE 34
11
10
VO2–
VO2+
M903
(LOADING)
M901
(SPINDLE)
M902
(SLED)
FOCUS/TRACKING COIL DRIVE,
SLED/SPINDLE/LOADING
MOTOR DRIVE
IC1
3
FOK
96
SQSO
97
SQCK
100
XRST
102
DATA
104
XLAT
105
CLOK
107
SENS
CD-L
81
AOUT1
86
AOUT2
R-CH
18 CD SQCK
15 CD XRST
15 CD XRST
14 CD DATA
13 CD XLAT
53 MEC_SELFSW
45 MEC_INSW
42 MEC_LIMIT
12 CD CLOK
11 CD SENS
108
SCLK
10 CD SCLK
113
GFS
8
CD GFS
114
C2PO
7
CD C2PO
115
SCOR
52 CD SCOR
81 X1
80 X0
MEC LOAD
43
MEC EJECT
44
CD
SYSTEM CONTROL
IC4
AUDIO INTERFACE
IC8
+1.5V REG
IC7
SYSTEM CONTROL
IC500 (1/3)
19 CD FOK
16 CD SQSO
DRON
41
SD1O
14
LRCK1B
19
LRCK1A
16
SD0O
11
BCK1B
18
BCK1A
15
CLCK
22
SRMSTB
41
RESET
2
STANDBY
3
BUCK
36
I2C SCL
7
I2C SDA
6
BUSO
28
SW2
(SELF)
46 MEC_DSW
SW1
(DOWN)
SW3
(DISC IN)
SW4
(LIMIT)
91
LMUT
22 CD LMUT
90
RMUT
23 CD RMUT
51
BU IN
75
RSTX
61
EJECT OK
67
MECON CHK
69
EMPH
32
DEC SDA
31
DEC SCL
30
DEC INT
29
DEC STBY
28
DEC XRST
27
DEC SSTBY
37
DEC XMUTE
65
DECON
63
MECON
64
CDON
66
ZMUTE
60
A ATT
PD1
E
F
LD
PD
FCS+
FCS–
TRK+
TRK–
PD2
LD DRIVE
Q1
+3.3V
CONTROL
Q5,6
+1.5V
CONTROL
Q2,3
• R-ch is omitted due to same as L-ch.
77
78
X1
16.9344MHz
X2
18.43MHz
XTAI
XTAO
66
BCK
60
BCKI
61
PCMDI
63
LRCK
62
LRCKI
65
PCMD
PANEL SW
M-ATT
BU IN
SYS RST
58
CD ON
VOUT
29
CDM ON
30
Z MUTE
MECH+6V
KEY BOARD
42
56
UNISI
25
RXD
57
UNISO
26
TXD
58
UNICLK
UNI SI
UNI SO
UNI CLK
50
BUS ON
BUS ON
68
CDON CHK
1
5
VDD
3
CE
SERVO 3.3V
+1.5V
VDDT+3.3V
BU 3.3V
MAIN
SECTION
MAIN
SECTION
A
B
3-2. BLOCK DIAGRAM — CD SECTION —
(Page 20)
(Page 20)
CDX-F5500N
20
20
CDX-F5500N
J1
(ANTENNA)
1 ANT
CDL
CDR
CD-L
TU-L
R-CH
3
R
AUDIO 8.3V
TUNER UNIT
TU1
6
S-METER
14
SDA
SYSTEM CONTROL
IC500 (2/3)
24
ACCIN 21
TELATT 23
AMPSTB 70
BEEP 85
CD
SECTION
A
CD
SECTION
B
3
11
CN700
J400
1
9
FL+
FL-
2
10
RL+
RL-
4
12
13
7
FR+
FR-
15
RR+
RR-
TEST
ACC
ATT
16 +B (BATT)
8 GND
R-CH
F901
10A
TU_ATT
BU3.3V
17
19
18
BATT
BATT
EEP_CKO
67
VSM
13
SCL
ATT
BATT
D493
59
TESTIN
DIAG
22
93
VOLATT
60
SOUND CONTROL
ELECTRONIC VOLUME
IC400
BUS-LCH
AP2
5
C2
9
B2
7
SDA
SCL
MUTE
CONT.
EVR
29
I2C_SIO
I2C_CKO
79
81
17
E2P-SDA
16
E2P-SCL
8
MUTE CON
7
TUN MUTE
11
VDD5V
10
VCC8.3V
68 EEP_SIO
64
TU_ATTIN
28
R-CH
25
29
AUDIO OUT FRONT
-5
L
R
-6
R-CH
5 AMP-R
27
35
37
34
33
31
30
6 ANT-R
BEEP
STB
FL
RL
SUB-L
4
SCL
2
SDA
CONT.
9
7
6
20
POWER AMP
IC300 (1/2)
MULTIPLE VOLTAGE
REGULATOR
IC300 (2/2)
VP2
VP1
VP1
• Signal path
: FM
: AM
: CD
• R-ch is omitted due to same as L-ch.
AUDIO OUT REAR
-3
L
R
-4
R-CH
BUS AUDIO IN
-1
L
R
-2
R-CH
12
BUIN
M-ATT
31
UNI CKO 6
4
L
OUTF2
23
OUTR2
22
SYSRST 37
RESET 19
+5V REG.
Q3
RESET
IC502
LINE MUTE
CONTROL
Q491,492
TEL
ATT
ATT
Q701
I2C
BUS
ACC
CHECK
Q702
MUTE
Q440
MUTE
Q450
11
MUTE
TONE
INPUT SELECTOR
EFFECT
OUTS2
17
MUTE
Q480
5
3
DIAG
AMP-REM
ANT-REM
B.UP+B
PANEL+B
MECH 6V
SERVO 3.3V
AUDIO +B
BU5V
PANEL+B
MECH 6V
SERVO 3.3V
AUDIO 8.3V
SERVO 3.3V
AUDIO 8.3V
VP
D302
D301
D603
D602
D351
D601
S103
RESET
BUS INTERFACE
IC600
MUTE
16
22
I2C
BUS
31
30
UNI SI
UNI SO
UNI CLK
BUS ON
BU IN
SYS RST
B/U C
10
RST
13
DATA IN
9
CLK IN
11
BUS IN
12
DATA OUT
8
1
2
BU5V
BU3.3V
+3.3V REG
IC501
3
2
UNI SI 5
UNI SO 4
BUS ON 36
BATT 3
RST 2
DATA I/O 6
4
5
6
5
6
1
7
8
2
3
3
CLK 4
BUS ON 1
BATTERY
CHECK
Q605
BUS ON
SWITCH
Q600,601
CN600
(BUS CONTROL IN)
3-3. BLOCK DIAGRAM — MAIN SECTION —
(Page 19)
(Page 19)
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