Sony CDX-C90R Service Manual ▷ View online
– 17 –
3-1. IC PIN DESCRIPTIONS
• IC5 CXP84640-011Q (CD SYSTEM CONTROL)
• IC5 CXP84640-011Q (CD SYSTEM CONTROL)
Pin No.
Pin Name
I/O
Pin Description
1 – 5
NCO
—
Not used in this set.
6
FP OPEN
I
Front panel open detection input
7
FP CLOSE
O
Front panel close control output
8
LINKOFF
I
Bus interface link input (Not used in this set.)
9
DRV OE
O
Focus/tracking coil/sled motor control output
10
D SW
I
Down switch input (SW4)
11 – 13
NCO
—
Not used in this set.
14
LM EJ
O
Loading motor control output
15
LM LOD
O
Loading motor control output
16
EMPH O
O
De-emphasis ON/OFF control output
17
CDMON
O
CD mechanism deck power control output
18
CD ON
O
CD power control output
19
A MUT
O
System attenuate control output
20
LD ON
O
Laser power ON/OFF control output
21
CD RST
O
CD system reset output
22 – 24
—
—
Not used in this set.
25
PH3
I
Not used in this set.
26
TSTIN0
I
Not used in this set.
27
TSTIN1
I
Not used in this set.
28
TST CLV
I
Not used in this set.
29
NCO
—
Not used in this set.
30
RESET
I
System reset input (“L” = Reset)
31
X IN
I
X’tal oscillator input of system clock. (10 MHz)
32
X OUT
O
X’tal oscillator output of system clock. (10 MHz)
33
GND
—
Analog GND
34
XT OUT
O
Not used in this set.
35
XT IN
I
Not used in this set.
36
AVSS
—
A/D converter GND
37
AVREF
I
A/D converter reference voltage input
38
TEP L
I
Not used in this set.
39
TEP H
I
Not used in this set.
40
NCO
—
Not used in this set.
41
PH2
I
Not used in this set.
42
SCLK
O
CD-TEXT data read clock output
43
ESPXQOK
O
XQOK signal output to DRAM controller.
44
ESPSDT
I
Serial data input from DRAM controller.
45
GRSRST
O
Reset signal output to DRAM controller.
46
GRSCOR
I
Sub-cord sync input from DRAM controller.
47
CD XLAT
O
CD signal process serial latch output
48
TX CLK
O
EEPROM serial clock output
49
TX DATA
O
EEPROM serial data output
50
UNISO
O
Not used in this set.
51
BUS CLK
I/O
Bus system serial clock input/output
52
BUS SI
I
Bus system serial interface input
53
BUS SO
O
Bus system serial interface output
54
F OK
I
Focus OK signal input
55
GFS
I
GFS signal detection input
56
SCOR
O
Sub-cord sync output
57
SENS
I
SENS signal input
58
—
I
Fixed at “H” in this set.
59
CD CKO
O
CD signal process serial clock output
SECTION 3
DIAGRAMS
– 18 –
Pin No.
Pin Name
I/O
Pin Description
60
BU.IN
I
Back-up power detection input
61
BUSON
I
Bus on control input
62
IN SW
I
Disc in switch input (SW1)
63
SELF SW
I
Self switch input (SW2)
64
TX CE
O
EEPROM chip enable output
65
SCK2
O
Sub Q read clock output
66
SI2
I
Sub Q 80 bit, PCM peak and level data 16 bit input
67
CD DATA
O
CD signal process serial data output
68
ESPXWRE
O
Write signal output to DRAM controller.
69
ESPXRDE
O
Read signal output to DRAM controller.
70
ESPXLT
O
Serial data latch output to DRAM controller.
71
ESPXSOE
O
XSOE signal output to DRAM controller.
72
VDD
—
Power supply
73
HIN
I
Fixed at “H” in this set.
74
TEXT.ON/OFF
I
Fixed at “H” in this set.
75
PH1
I
Not used in this set.
76
FBTBSEL
I
Not used in this set.
77
CDOSEL
I
Not used in this set.
78 – 80
—
—
Not used in this set.
– 19 –
• IC501 CXD2548R (DIGITAL SERVO, DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Pin Description
1
SYSM
I
System mute input (Not used.)
2
RMUT1
O
R-ch, “0” detection output. (“H” : ON, “L” : OFF) (Not used.)
3
LMUT2
O
L-ch, “0” detection output. (“H” : ON, “L” : OFF) (Not used.)
4
CKOUT
O
Master clock frequency division output (Not used.)
5
VDD0
—
Digital power supply
6
SBSO
O
Serial output of sub-P to W.
7
EXCK
I
Clock input for SBSO read output.
8
SQCK
I
Clock input for SQSO read output.
9
SQSO
O
SubQ 80 bit, PCM peak and level data 16 bit output.
10
SENS
O
SENS output. Output to CPU.
11
SCLK
I
Clock input for SENS real data read.
12
DATA
I
Serial data input from CPU.
13
XLAT
I
Latch input from CPU. Latch serial data at the falling edge.
14
CLOK
I
Serial data transfer clock input from CPU.
15
XRST
I
System reset (“L” : Reset)
16
ACDT
O
Not used.
17
PWM1
I
External control input of spindle motor.
18
XLON
O
Microcomputer extension interface (Output) (Not used.)
19
SPOA
I
Microcomputer extension interface (Input A) (Not used.)
20
WFCK
O
WFCK (Write Flame Clock) output
21
GTOP
O
GTOP output
22
XUGF
O
XUGF output (Not used.)
23
XPCK
O
XPLCK output (Not used.)
24
GFS
O
GFS output
25
RFCK
O
RFCK output
26
C2PO
O
C2PO output (Not used.)
27
XROF
O
XROF output
28
SCOR
O
“H” output at either detection, sub code sync S0 or S1.
29
MNT0
O
MNT0 output (Not used.)
30
MNT1
O
MNT1 output (Not used.)
31
MNT3
O
MNT3 output (Not used.)
32
VSS1
—
Digital GND
33
DOUT
O
Digital-Out output
34
ATSK
I
For anti-shock.
35
MIRR
O
Mirror signal output (Not used.)
36
DFCT
O
Diffect signal output (Not used.)
37
FOK
O
Focus OK signal output
38
VDD1
—
Digital power supply
39
VPCO1
O
Charge pump output for wideband EFM PLL.
40
VPCO2
O
VCO2 charge pump output for wideband EFM PLL.
41
VCK.I
I
VCO2 oscillator input for wideband EFM PLL.
42
V16M
O
VCO2 oscillator output for wideband EFM PLL.
43
VCTL
I
VCO2 control input for wideband EFM PLL.
44
PCO
O
Charge pump output for master PLL.
45
FILO
O
Filter output for master PLL (Slave = digital PLL).
46
FILI
I
Filter input for master PLL.
47
AVSS4
—
Analog GND
48
CLTV
I
VCO control voltage input for master.
49
AVDD4
—
Analog power supply
50
RFAC
I
EFM signal input
51
BIAS
I
Asymmetry circuit constant current input
52
ASY.I
I
Asymmetry comparate voltage input
– 20 –
Pin No.
Pin Name
I/O
Pin Description
53
ASY.O
O
EFM full-swing output (“L” : VSS, “H” : VDD)
54
VC
I
Center voltage input
55
FE
I
Focus error signal input
56
SE
I
Sled error signal input
57
TE
I
Tracking error signal input
58
CE
I
Center error signal input
59
RFDC
I
RF signal input
60
RFC
I
Condenser connection pin for LPF time constant of RF signal.
61
ADIO
O
OP amplifier output (Not used.)
62
AVSS3
—
Analog GND
63
IGEN
I
Current source reference resistor connection for OP amplifier.
64
AVDD3
—
Analog power supply
65, 66
TES2, 3
I
TEST pin (Fixed at “L”.)
67
VSS2
—
Digital GND
68
TEST
I
TEST pin (Fixed at “L”.)
69
SFDR
O
Sled drive output
70
SRDR
O
Sled drive output
71
TFDR
O
Tracking drive output
72
TRDR
O
Tracking drive output
73
FFDR
O
Focus drive output
74
FRDR
O
Focus drive output
75
VDD2
—
Digital power supply
76
COUT
O
Track number count signal output (Not used.)
77
LOCK
O
Not used.
78
MDS
O
Servo control output of spindle motor. (Not used.)
79
MDP
O
Servo control output of spindle motor.
80
SSTP
I
Disc most inner track detection signal input
81
FSTO
O
2/3 frequency division output of pins 103 and 104.
82
FSTI
I
Reference clock input for digital servo.
83
XTSL
I
X’tal select input (“L” : 16.9344 MHz)
84
C4M
O
4.2336 MHz output
85
WDCK
O
D/A interface. Word clock f = 2Fs
86
VDD3
—
Digital power supply
87
LRCK
O
D/A interface. LR clock f = Fs
88
LRCKI
I
LR clock input to DAC. (48 bit slot) (Not used.)
89
PCMD
O
D/A interface. Serial data (2’s COMP, MSB first)
90
PCMDI
I
Audio data input to DAC. (48 bit slot) (Not used.)
91
BCK
O
D/A interface. Bit clock
92
BCKI
I
Bit clock input to DAC. (48 bit slot) (Not used.)
93
EMPH
O
Not used.
94
EMPHI
I
De-emphasis ON/OFF of DAC. (“H” : ON, “L” : OFF) (Not used.)
95
VSS3
—
Digital GND
96
AVSS1
—
L-ch, Analog GND.
97
AVDD1
—
L-ch, Analog power supply.
98
AOUT1
O
L-ch, Analog output. (Not used.)
99
AIN1
I
L-ch, OP amplifier input. (Not used.)
100
LOUT1
O
L-ch, LINE output. (Not used.)
101
AVSS1
—
L-ch, Analog GND.
102
XVDD
—
Analog power supply for master clock.
103
XTAI
I
X’tal oscillator input of master clock (16.9344 MHz).
104
XTAO
O
X’tal oscillator output of master clock. (Not used.)
105
XVSS
—
Analog GND for master clock.
106
AVSS2
—
R-ch, Analog GND.
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