Sony CDX-828 Service Manual ▷ View online
CDX-828
– 17 –
– 18 –
7-1.
BLOCK DIAGRAM – SERVO Section –
SECTION 7
DIAGRAMS
XROF
M
M
M
A
B
D
F
E
C
I-V AMP
DETECTOR
39
38
2
1
12
13
27
OUT+
OUT–
SLO
OUT–
OUT+
OUT+
OUT–
SPINDLE
MOTOR DRIVE
M101
(SPINDLE)
SLED
MOTOR DRIVE
26
M102
(SLED)
FOCUS
COIL DRIVE
TRACKING
COIL DRIVE
OUT+
OUT–
OUT–
19
24
4
10
IN
IN
IN
IN
SLP
FOCUS/TRACKING COIL DRIVE,
SPINDLE/SLED MOTOR DRIVE
IC51
16
14
SLED
AMP
LD
PD
LASER DIODE
OPTICAL PICK-UP
(KSS-521A)
2-AXIS
DEVICE
(FOCUS)
(TRACKING)
33
32
27
44
23
22
20
21
19
23
RF AMP,
FOCUS/TRACKING
SERVO
IC11 (1/2)
FOCUS OK
COMPARATOR
MIRR
AMP
DEFECT
AMP
FOCUS OK
AMP
IIL DATA REGISTER
40
38
FILTER
42
39
FILO
PCO
CLTV
FILI
DIGITAL PLL
ASYMMETRY
CORRECTION
CORRECTION
EFM
DEMODULATOR
DIGITAL
OUT
ERROR
CORRECTOR
16K
RAM
INTERNAL BUS
SUB-CODE
PROCESSOR
SERVO AUTO SEQUENCER
DIGITAL CLV
17
15
52
54
50
100
16
WDCK
8 7 9 10 12 11 75 76 77
61
26
28
14
13
1
7
4
5
4
5
CH.F
CH.R
CHUCKING
MOTOR DRIVE
CHUCKING MOTOR DRIVE
IC52
FIN
RIN
OUT1
OUT2
SW11
(CHUCKING END DETECT)
LOAD1
LOAD2
SW12
(SAVE END DETECT)
SW1
(LIMIT)
M103
(CHUCKING)
41
42
36
37
1
40
45
2
47
17
16
6
25
24
13
+
PD1
PD1 I-V AMP
RFO
RF
46
ASYI
47
ASYO
FOK
DATO
CLKO
XLTO
SEIN
CNIN
CNIN
C.OUT
FOK
SUBQ
SCLK
SENS
CD.DATA
CD.CLK
CD.XLT
SCOR
MON
MDP
MDS
29
LOCK
64
SQSO
SQCK
SENS
DATA
CLOCK
XLAT
SCOR
SBSO
EXCK
GFS
GTOP
WFCK
EMPH
C4M
XRST
RFI
FOK
DATA
CLK
SENS1
26
SENS2
C.OUT
XLT
LOCK
XRST
PD2 I-V AMP
PD2
TTL
IIL
FEO
TEO
PD
FEI
FEO
TAO
TEI
TTL
IIL
TTL
IIL
FOCUS
ERROR
AMP
RF
SUMMING
AMP
TRACKING
ERROR
AMP
TRACKING PHASE
COMPENSATION
FOCUS PHASE
COMPENSATION
AUTOMATIC
POWER CONTROL
Q11
I-V
AMP
LD
AMP
PD
AMP
FE BIAS
RV14
F
E
LD
89
XTAI
PCMD
71
D.OUT
BCKO
LRCK
63
C2PO
62
49
RFCK
RFCK
DATA
PCMD
BCK
LRCK
WDCK
A
XRST
RESET
ON : When completion of the disc
chucking operation.
ON : When the optical pick-up
is inner position.
SLED SERVO
IC11 (2/2)
05
DIGITAL SIGNAL PROCESSOR,
CLV SERVO
IC101
SYSTEM CONTROLLER
IC201 (1/3)
ON : When completion of the disc
chucking operation.
• SIGNAL PATH
(Page 19)
(Page 19)
(Page 19)
: CD PLAY (ANALOG OUT)
: CD PLAY (DIGITAL OUT)
27
FOCUS
GAIN
CPU INTERFACE
D/A
INTERFACE
CLOCK
GENERATOR
EDGE DETECT
IC403 (1/2)
70
74
72
58
1
2
7
IC403
(2/2)
GTOP
WFCK
C4M
XROF
SCLK
SBSO
C16M
22
SENS2
8
54
52
51
23
23
67
65
66
63
GFS 24
21
C
E
(Page 19)
(Page 20)
D
RFCK, GTOP, WFCK,
C4M, XROF,
DATA, PCMD, BCK,
LRCK, WDCK
(Page 19)
B
H
SCOR
(Page 19)
G
DATA, CLOCK
DATA
CLOCK
(Page 19)
F
LIM.SW 9
7
6
CDX-828
– 19 –
– 20 –
7-2.
BLOCK DIAGRAM – MAIN Section –
11
9
12
13
7
6
5
3
8
61
47 48 46 50
29
46
76
77
25
27
45 44 49 59
16
19
17
18
20
A
B
DATA, PCMD, BCK,
LRCK, WDCK
LRCK, WDCK
PCMD
BCK
LRCK
LRCK
WDCK
DATA
DATI
BCKI
LRCI
WDCI
4
DIN
RFCK
WFCK
XROF
C4M
C4M
XROI
XROI
SCOR
RFCK
GTOP
RFCK, GTOP, WFCK,
C4M, XROF
C4M, XROF
WFCK
WFCK
2
31, 30, 33, 32
1, 2, 24, 25
25 – 22, 40 – 36, 27
9 – 12, 14 – 18, 5
DSP
INTERFACE
DATA
LINKING
CONTROL
SELECTOR
D-RAM INTERFACE
READ/WRITE
BASE
COUNTER
VWA
ADDRESS MONITOR
CPU INTERFACE
SDTI
1
GRST
60
GSCR
SCK
DATA
GRSCOR
79
CSI
78
CSO
77
7 6 5
CCLK
CSI
76
REQ
74
BUSY
4 56
BUSY
CCLK
SCOR
WFCK
8
9
SCLK
SSI
SDTI
41 42 28 26
CLOCK
SDTO
XLT
XRDE
XWRE
XSOE
XQOK
SYSTEM CONTROLLER
IC201 (2/3)
D/A CONVERTER
IC601
05
CD TEXT DECODER
IC501
D-RAM
IC402
S-RAM
IC502
A0 – A9
D1 – D4
XTAI
TIMING
GENERATOR
D/A
CONVERTER
INTERFACE
SERIAL
INPUT
INTERFACE
DE-EMPHASIS
CONTROL
CPU
INTERFACE
CLOCK OSC/
DIVIDER
CLOCK
BUFFER
IC603
MUTING
CONTROL SWITCH
Q601, 602
LOW-PASS
FILTER
IC602 (1/2)
MUTING
Q603
LOW-PASS
FILTER
IC602 (2/2)
PWM
INTER-
POLATOR,
∆Σ
MODULATOR
DATA
D OUT
BCK
LRCK
DATA
BCK
LRCK
D-RAM CONTROLLER
IC401
DIGITAL
OUT
BUFFER
IC604
(Page 18)
D
SCLK
IC503
SBSO
(Page 18)
E
(Page 18)
G
SCOR
(Page 18)
F
DATA, CLOCK
(Page 18)
H
(Page 18)
(Page 18)
C
C16M
(Page 18)
I
(Page 22)
J
BU CHECK
(Page 22)
RESET
XRST
35
29
34
28
22
3
23
4
20 27
62 63
XRAS
XCAS
XWE
XOE
XRAS
D1 – D4
A0 – A9
11 – 13, 15 – 19
10 – 3, 25, 24, 21, 23, 2, 26, 1
11 – 18, 64 – 69, 74
DO0 – DO7
20 – 27
DATA0 – DATA7
A0 – A14
ADD0 – ADD14
XCAS
XWE
CE
CE
WE
WE
XOE
ESPXLT
XRDE
XWRE
XSOE
XQOK
GRSRT
CSO
REQ
OPTICAL
TRANSCEIVER
IC801
SW801
(ANALOG/DIGITAL SELECT)
BUCK
D501
X601
16.9344MHz
AOUTL
AOUTR
A/D.SW
XT
AL
EXT
AL
EMP
DFS
PD
EMP
ML
D/A.RESET
XTO
XTI
56
28
78
12
11
6
44
45
A.MUTE
43
47
RESET
75
4
5
18
17
8
7
9
X501
10MHz
30
29
MUTING
Q604
R
L
CN901 (1/2)
ANALOG OUT
IC801
DIGITAL OUT
RST
ANALOG
DIGITAL
GTOP
RESET
• SIGNAL PATH
: CD PLAY (ANALOG OUT)
: CD PLAY (DIGITAL OUT)
CDX-828
– 21 –
– 22 –
7-3.
BLOCK DIAGRAM – BUS CONTROL /POWER SUPPLY Section –
2
13
8
7
69
31
32
30
I
B.UP
DATA
CLK
BUSON
RST
SCK
SO
SI
68
61
BU.CHK
CD.ON
MAG.SW
MGLK
BUS.ON
W.UP
EJECT
EXTAL
XTAL
7
5
4
6
2
REGULATOR
Q303
B+ SWITCH
Q305
+5V
REGULATOR
IC305
+5V
REGULATOR
IC307
+8V
REGULATOR
IC306
MICON +5V
DAC +5V
+8V
LOW-PASS FILTER
(IC602) B+
MICON +5V
D313
RESET SIGNAL
GENERATOR
IC304
X201
8MHz
SERVO +5V
Q304
MICON +5V
MICON +5V
RST
05
SYSTEM CONTROLLER
IC201 (3/3)
(Page 20)
J
BU CHECK
(Page 20)
LEVEL SHIFT
D307
BATTERY
CHECK
Q301, 302
D308
D306
+9V
REGULATOR
IC303
REFERENCE VOLTAGE
SWITCH
Q201
LINEAR POSITION
SENSOR
D309
SERVO +9V
D311
12
1
4
11
9
6
10
M
1
7
4
5
70
58
ELV.R
ELV.F
ELEVATOR
MOTOR DRIVE
EEPROM
IC202
ELEVATOR MOTOR DRIVE
IC301
FIN
RIN
5
6
12
11
EE.DATA
EE.CLK
SDA
SCL
OUT1
OUT2
M104
(ELEVATOR)
ELV.ON
MCK
RV201
ELEVATOR HEIGHT
SENSOR
RV202
38
EHS 39
AVREF 37
RESET
SWITCH
RST
BUSON IN
CLK
DATA
LOF
SCK
SO
SI
BUSON OUT
BUSON OUT
RESET
55
48
50
49
62
64
SW301
6
57
SW201
MAGAZINE EJECT
END DETECT
SW202
MAGAZINE IN/OUT
DETECT
BUS INTERFACE
(FOR SONY BUS)
IC302
60
CN901 (2/2)
(FOR SONY BUS)
CONTROL
RESET
• Circuit Boards Location
JACK board
MAIN board
RF board
SW board
DIGITAL OUT board
– 23 –
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