Sony CDX-757MX Service Manual ▷ View online
37
CDX-757MX
SCK
1 2 3
7 8
4
5
6
SERIAL
INPUT
INTERFACE
10
9
BCK
DATA
LRCK
VOUTL
VOUTR
DGND
VDD
VCC
VCOM
AGND
FUNCTION
CONTROL
INTERFACE
SYSTEM
CLOCK
MANAGER
8 TIME OVER
SAMPLING
DIGITAL FILTER
WITH
FUNCTION
CONTROLLER
ENHANCED
MULTI-LEVEL
DELTA-SIGMA
MODULATOR
D/A
CONVERTER
D/A
CONVERTER
OUTPUT AMP AND
LOW-PASS FILTER
LOW-PASS FILTER
OUTPUT AMP AND
LOW-PASS FILTER
LOW-PASS FILTER
ZERO DETECT
POWER SUPPLY
12
11
ZEROL
ZEROR
15
14
ML
MC
16
13
MD
SYSTEM
CLOCK
1
2
3
4
5
6
7
8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DATA OUT
DATA IN
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON IN
BUS ON OUT
RESET
RESET
SWITCH
1
2
2
3
4
5
6
7
8
9
10
VCC
IN2
S-GND
IN1
NC
NC
OUT2
NC
P-GND
OUT1
CONTROL
CIRCUIT
MOTOR
DRIVE
CIRCUIT
BUFFER
BUFFER
IC301
LB1930M-TLM
IC302
BA8272AFV-E2
IC501
PCM1748E/2K
38
CDX-757MX
IC601
CXD9684R-004
2
1
RESET
MIMD
3
AD0
4
AD1
5
MIDIO
6
MICK
7
AD2
8
VDDT
9
SDO
10 AD3
11 AD4
12 SDI0
13 BCKIA
14 LRCKIA
15 AD5
16 CE
17
OE
18
VDD
19
STANDBY
20
VSS
21
VSSL
22
VRAL
23
LO
24
VDAL
25
VDAR
26
RO
27
VRAR
28
VSSR
29
TESTP
30
CKS
31
AD12
32
AD11
64
VSSX
63
XO
62
XI
61
V
DDX
60
CKO
59
V
DDP
58
VCOI
57
PDO
56
VSSP
55
IO7
54
IO6
53
IO5
52
VDD
51
IO4
50
IO3
49
IO2
48
VSS
47
IO1
46
IO0
45
AD15
44
AD16
43
WR
42
AD14
41
AD13
40
VSS
39
REQ
38
AD6
37
AD7
36
AD8
35
VDDT
34
AD9
33
AD10
TIMING
GENERATOR
VCO
PROG.
START
DIT
GENERAL
INPUT PORT
INTERRUPT
CONTROL
SRAM I/F
I-BUS
TIMER
DAC
DAC
BUS
SWITCH
Y-POINTER
REGISTER
X-POINTER
REGISTER
C-POINTER
REGISTER
ERAM
2k WORD
XRAM
4k WORD
YRAM
4k WORD
CROM
4k WORD
x3
ALU
A2
A3
AX
AY
ROUND & LIMIT
MAC
A0
A1
MX
MY
MZ
IINSTRUCTION
DECODER
PROM
4kx2+2k
=10k WORD
40 BIT
PRAM
256 WORD
PROGRAM
CONTROL
Y-BUS
X-BUS
GENERAL
OUTPUT
PORT
FLAG
ADDRESS
CALC.
2 SETS
MICROCOM.
I/F
AUDIO
I/F
REGISTER
X0 X1 X2
Y0 Y1 Y2
Y0 Y1 Y2
ROUND & LIMIT
39
CDX-757MX
6-14.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC201 HD6432238RWN21TEIV (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
TEST
I
Test mode setting terminal “L”: test mode Not used
2
DECXRST
O
Reset signal output to the CD-ROM/MP3 decoder “L”: reset
3
DECSTBY
O
Standby mode control signal output to the CD-ROM/MP3 decoder “H”: standby
4
FOK
I
Focus OK signal input from the DSP “L”: NG, “H”: OK
5
GFS
I
Guard frame sync signal input from the DSP “L”: NG, “H”: OK
6
SCLK
O
Serial data reading clock signal output to the DSP
7
SENS
I
Internal status signal (sense signal) input from the DSP
8
CDCLK
O
Serial data transfer clock signal output to the DSP
9
CDLAT
O
Serial data latch pulse signal output to the DSP
10
CDDAT
O
Serial data output to the DSP
11
XRST
O
System reset signal output to the DSP “L”: reset
12
CVCC
—
Power supply terminal (+3.3V) (for system)
13
NC
O
Not used
14
VSS
—
Ground terminal
15
XQOK
O
Subcode Q OK pulse signal output to the DSP
16
XRDE
O
Read enable signal output to the DSP
17
XWRE
O
Write enable signal output to the DSP
18
DAC-DATA
O
Mode control data output to the D/A converter
19
DAC-CLK
O
Mode control data transfer clock signal output to the D/A converter
20
DAC-LAT
O
Mode control data latch pulse signal output to the D/A converter
21
ESPSEL
I
ESP mode setting terminal “L”: ESP on (fixed at “L” in this set)
22
TEXTSEL
I
CD text mode setting terminal “L”: CD text on (fixed at “L” in this set)
23
CFSEL
I
Custom file on/off setting terminal “L”: custom file on (fixed at “L” in this set)
24
DOUT SEL
I
Input terminal for digital out on/off setting “L”: digital out on Not used
25
MAG-SW
I
Magazine detect switch input terminal Not used
26
MUTE
O
Audio line muting on/off control signal output “H”: muting on
27, 28
NC
O
Not used
29
CDON
O
D/A convert and servo sections power supply on/off control signal output “H”: power on
30
EVON
O
Mechanism deck section power supply on/off control signal output “H”: power on
31
PCTX
O
PC connecting output terminal for UART
32
PCRX
I
PC connecting input terminal for UART
33 to 35
NC
O
Not used
36
ELVF
O
Motor drive signal (elevator up direction) output to the elevator motor drive
37
ELVR
O
Motor drive signal (elevator down direction) output to the elevator motor drive
38
SCOR
I
Subcode sync (S0+S1) detection signal input from the DSP
39
NC
O
Not used
40
GRSCOR
I
Subcode sync (S0+S1) detection signal input from the DSP
41
NC
O
Not used
42
AVSS
—
Ground terminal (for A/D converter)
43 to 49
NCI
I
Not used
50
EHS
I
Elevator height position detection signal input from the elevator height sensor (A/D input)
51
NCI
I
Not used
52
MCK
I
Input of detection signal for the fine adjustment (elevator height (address) adjustment) of elevator
height position (A/D input)
height position (A/D input)
53
VREF
I
Reference voltage (+3.3V) input terminal (for A/D converter)
40
CDX-757MX
Pin No.
Pin Name
I/O
Description
54
AVCC
—
Power supply terminal (+3.3V) (for A/D converter)
55, 56
MD0, MD1
I
Setting terminal for the CPU operational mode “H”: single chip mode (fixed at “H” in this set)
57
OSC2
O
Sub system clock output terminal Not used
58
OSC1
I
Sub system clock input terminal Not used (fixed at “L”)
59
RES
I
System reset signal input from the SONY bus interface and reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
60
NMI
O
Not used (fixed at “H”)
61
STBY
O
Standby mode control signal output terminal Not used (fixed at “H”)
62
VCC
—
Power supply terminal (+3.3V)
63
XTAL
I
Main system clock input terminal (12.288 MHz)
64
VSS
—
Ground terminal
65
EXTAL
O
Main system clock output terminal (12.288 MHz)
66
FEW
I
Flash memory data write enable signal input terminal
67
MD2
I
Setting terminal for the CPU operational mode “H”: single chip mode (fixed at “H” in this set)
68
FL BOOT
I
Flash memory data write control signal input terminal “L” active
69
FL W
O
Flash memory data write control signal output (connecting FEW (pin 66))
70, 71
NC
O
Not used
72
MGLK-SW
I
Magazine in/out detect switch input terminal “L”: magazine in
73
DECINT
I
Interrupt signal input from the CD-ROM/MP3 decoder
74
NC
O
Not used
75
EJECT
I
Eject switch input terminal “L” active
76
SO
O
Serial data output to the SONY bus interface
77
SI
I
Serial data input from the SONY bus interface
78
SCLK
I
Serial data transfer clock signal input from the SONY bus interface
79
EEDATA
I/O
Two-way data bus with the EEPROM
80
SDA
I/O
I2C interface data input/output with the CD-ROM/MP3 decoder
81
SCL
O
I2C interface data transfer clock signal output to the CD-ROM/MP3 decoder
82
EECLK
O
Serial data transfer clock signal output to the EEPROM
83
NC
O
Not used
84
SQSO
I
Subcode Q data input from the DSP
85
SQCK
O
Subcode Q data reading clock signal output to the DSP
86 to 89
NC
O
Not used
90
R/RW SEL
O
CD-ROM/RW selection signal output “L”: CD-RW, “H”: CD-ROM
91
BUSON
I
Bus on/off control signal input from the SONY bus interface “L”: bus on
92
BUCHK
I
Battery detection signal input “H”: low battery (Normally: “L”)
93, 94
NC
O
Not used
95
LOADF
O
Motor drive signal (load chucking direction) output to the chucking motor drive
96
LOADR
O
Motor drive signal (save direction) output to the chucking motor drive
97
SINGLE
I
Setting terminal for the single disc/multiple discs mode
“L”: single disc mode, “H”: multiple discs mode (fixed at “H” in this set)
“L”: single disc mode, “H”: multiple discs mode (fixed at “H” in this set)
98
LOAD SW
I
Chucking end detect switch input terminal
“L”: When completion of the disc chucking operation
“L”: When completion of the disc chucking operation
99
SAVE SW
I
Save end detect switch input terminal
“L”: When completion of the disc save operation
“L”: When completion of the disc save operation
100
LIM SW
I
Sled limit in detect switch input terminal
“L”: When the optical pick-up is inner position
“L”: When the optical pick-up is inner position
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