Sony CDX-656 / CDX-656X Service Manual ▷ View online
29
CDX-656/656X
– MAIN Board –
IC101
CXD3017Q
TE
RFDC
CE
IGEN
AVSS0
ADIO
AVDD0
CLTV
FILO
AVSS3
VSS
AVDD3
DOUT
VDD
PCO
FILI
ASYO
ASYI
RFAC
BIAS
SSTP
DFCT
MIRR
MDP
LOCK
FOK
SFDR
VSS
TEST
FRDR
FE
VC
VC
COUT
SE
XTSL
TES1
SRDR
TFDR
FFDR
TRDR
TRDR
2
1
70
71
68
69
66
67
64
65
62
61
63
73
74
72
75
76
77
78
79
80
4
XRST
3
SQCK
SQSO
5
9
8
7
6
56
60
53
54
55
59
57
58
51
52
48
49
50
47
44
45
46
43
41
42
XLAT
CLOK
SENS
SYSM
DATA
XUGF
XPCK
GFS
C2PO
WFCK
10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
32
33
30
31
36
37
34
35
39
40
38
28
27
29
SPOA
ATSK
SCLK
VDD
SCOR
SPOB
XLON
XTAI
XVDD
EMPH
AVDD1
AOUT1
AIN1
XTAO
XVSS
XVSS
AIN2
AOUT2
AVDD2
RMUT
LOUT2
LOUT1
BCK
LRCK
PCMD
LMUT
AVSS1
AVSS2
CPU
INTERFACE
SERVO AUTO
SEQUENCER
SERIAL IN
INTERFACE
OVER SAMPLING
DIGITAL FILTER
3rd ORDER
NOISE SHAPER
PWM
PWM
EFM
DEMODULATOR
TIMING
LOGIC
DIGITAL
OUT
D/A
INTERFACE
DIGITAL
PLL
ASYMMETRY
CORRECTOR
CLOCK
GENERATOR
MIRR, DFCT,
FOK
DETECTOR
DIGITAL
CLV
SUBCODE
PROCESSOR
SERVO
INTERFACE
SERVO DSP
FOCUS
SERVO
SERVO
TRACKING
SERVO
SLED
SERVO
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING
PWM GENERATOR
SLED PWM
GENERATOR
16K
RAM
ERROR
CORRECTOR
INTERNAL BUS
A/D
CONVERTER
OPERATIONAL
AMPLIFIER
ANALOG SWITCH
IC301
LB1930M-TLM
1
2
2
3
4
5
6
7
8
9
10
VCC
IN2
S-GND
IN1
NC
NC
OUT2
NC
P-GND
OUT1
CONTROL
CIRCUIT
MOTOR
DRIVE
CIRCUIT
BUFFER
BUFFER
IC302
BA8272AFV-E2
1
2
3
4
5
6
7
8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DATA OUT
DATA IN
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON IN
BUS ON OUT
RESET
RESET
SWITCH
2
VOUT
3
GND
1
VIN
4
CONT
CONTROL
IC304
NJM2395AF08
IC305
NJM2395AF05
30
CDX-656/656X
6-12.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC201 MB90473PFV-G-111-BNDE1 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1, 2
RAMA5, RAMA6
O
Address signal output terminal Not used
3
ELVR
O
Motor drive signal (elevator down direction) output
4
ELVF
O
Motor drive signal (elevator up direction) output
5
LOADF
O
Motor drive signal (load chucking direction) output
6
LOADR
O
Motor drive signal (save direction) output
7, 8
RAMA7, RAMA12
O
Address signal output terminal Not used
9
VSS
—
Ground terminal
10
RAMA14
O
Address signal output terminal Not used
11
RAMWE
O
Write enable output terminal Not used
12 to15
RAMA13, RAMA8,
RAMA9, RAMA11
O
Address signal output terminal Not used
16
UNI SI
I
Serial data input from the SONY bus interface
17
UNI SO
O
Serial data output to the SONY bus interface
18
UNI CK
I
Serial data transfer clock signal input from the SONY bus interface
19
LEDDAT
O
Not used
20
LEDCLK
O
Not used
21
VCC
—
Power supply terminal (+3.3V)
22
LEDLAT
O
Not used
23
CDON
O
D/A converter and servo section power supply on/off control signal output “H”: power on
24
ELVON
O
Mechanism deck section power supply on/off control signal output “H”: power on
25
RX
I
Input terminal at the flash memory data write mode Not used
26
TX
O
Output terminal at the flash memory data write mode Not used
27
NC
O
Not used
28
EECLK
O
Serial data transfer clock signal output to the EEPROM Not used
29
FL BOOT
I
Flash memory data write control signal input terminal “L” active Not used
30, 31
NC
O
Not used
32
EEDAT
I/O
Two-way data bus with the EEPROM Not used
33
AVCC
—
Power supply terminal (+3.3V) (for A/D converter)
34
AVRH
I
Reference voltage (+3.3V) input terminal (for A/D converter)
35
AVSS
—
Ground terminal (for A/D converter)
36
EHS
I
Elevator height position detection signal input from the elevator height sensor (A/D input)
37
MCK
I
Input of detection signal for the fine adjustment (elevator height (address) adjustment) of elevator
height position (A/D input)
height position (A/D input)
38, 39
KEY0, KEY1
I
Not used
40
VSS
—
Ground terminal
41
FOK
I
Focus OK signal input “H”: OK
42
GFS
I
Guard frame sync signal input “H”: OK
43
SCLK
O
Serial data reading clock signal output to the CXD3017Q
44
SENS
I
Internal status signal (sense signal) input
45
BUSON
I
Bus on/off control signal input from the SONY bus interface “H”: bus on
46
BUCHK
I
Battery detection signal input “L”: battery on
47, 48
MD0, MD1
I
Setting terminal for the CPU operational mode (fixed at “H” in this set)
49
MD2
I
Setting terminal for the CPU operational mode (fixed at “L” in this set)
50
EJECT SW
I
Eject switch input terminal “L” active
51
MAGLK SW
I
Magazine detect switch input terminal “L”: magazine is set
31
CDX-656/656X
Pin No.
Pin Name
I/O
Description
52
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD3017Q
53
GRSCOR
I
Subcode sync (S0+S1) detection signal input terminal Not used
54
NC
O
Not used
55
HS
O
Normal/high speed playback control signal output terminal
“L”: high speed playback Not used
“L”: high speed playback Not used
56
SQSO
I
Subcode Q data input from the CXD3017Q
57
NC
O
Not used
58
SQCK
O
Subcode Q data reading clock signal output to the CXD3017Q
59
CDCLK
O
Serial data transfer clock signal output to the CXD3017Q
60
CDLAT
O
Serial data latch pulse signal output to the CXD3017Q
61
CDDAT
O
Serial data output to the CXD3017Q
62
XRST
O
System reset signal output to the CXD3017Q “L”: reset
63
XQOK
O
Subcode Q OK pulse signal output terminal Not used
64
XRDE
O
D-RAM read enable signal output terminal Not used
65
XWRE
O
D-RAM write enable signal output terminal Not used
66
EMPH
O
Emphasis control signal output “H”: emphasis on
67
MUTE
O
Audio line muting on/off control signal output “H”: muting on
68
RAMA10
O
Address signal output terminal Not used
69
RAMCS
O
Chip select enable output terminal Not used
70 to 74
RAMIO7 to
RAMIO3
I/O
Two-way data bus terminal Not used
75
RESET
I
System reset signal input from the SONY bus interface and reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
76
RAMIO2
I/O
Two-way data bus terminal Not used
77
X1A
O
Sub system clock output terminal Not used
78
X0A
I
Sub system clock input terminal Not used
79
VSS
—
Ground terminal
80
X0
I
Main system clock input terminal (4 MHz)
81
X1
O
Main system clock output terminal (4 MHz)
82
VCC
—
Power supply terminal (+3.3V)
83, 84
RAMIO1,
RAMIO0
I/O
Two-way data bus terminal Not used
85 to 88
RAMA0 to
RAMA3
O
Address signal output terminal Not used
89
SINGLE
I
Setting terminal for the single disc/multiple discs mode
“L”: single disc mode, “H”: multiple discs mode fixed at “H”
“L”: single disc mode, “H”: multiple discs mode fixed at “H”
90
6/10 SEL
I
Setting terminal for the 6 discs changer/10 discs changer model
“L”: 10 discs changer model, “H”: 6 discs changer model Not used
“L”: 10 discs changer model, “H”: 6 discs changer model Not used
91
CFSEL
I
Custom file on/off setting terminal “L”: custom file on fixed at “H”
92
TEXTSEL
I
CD text mode setting terminal
“L”: CD text on, “H”: does not display track name fixed at “H”
“L”: CD text on, “H”: does not display track name fixed at “H”
93
ESPSEL
I
ESP mode setting terminal “L”: ESP on Not used
94
TEST
I
Test on/off setting terminal “L”: test mode Nomally fixed at “H”
95
MAG SW
I
Magazine in/out detect switch input terminal Not used
96
SAVE SW
I
Save end detect switch input terminal
“L”: When completion of the disc save operation
“L”: When completion of the disc save operation
32
CDX-656/656X
Pin No.
Pin Name
I/O
Description
97
LOAD SW
I
Chucking end detect switch input terminal
“L”: When completion of the disc chucking operation
“L”: When completion of the disc chucking operation
98
LIM SW
I
Sled limit in detect switch input terminal
“L”: When the optical pick-up is inner position
“L”: When the optical pick-up is inner position
99
RW SEL
O
CD-ROM/RW selection signal output “L”: CD-RW, “H”: CD-ROM
100
RAMA4
O
Address signal output terminal Not used
Click on the first or last page to see other CDX-656 / CDX-656X service manuals if exist.