Sony CDX-616 Service Manual ▷ View online
– 41 –
• IC Block Diagrams
– RF Board –
– RF Board –
IC11
CXA1992BR
FZC
VC
TDFCT
TZC
ATSC
TEI
LPFI
TEO
VEE
EI
E
F
FE
BIAS
SL P
SL M
SL O
ISET
VCC
XRST
DATA
DATA
XLT
CLK
CLK
LOCK
SENS2
SENS1
C. OUT
VCC
DFCTO
IFB1 – IFB6
BAL1 – BAL4
TOG1 – TOG4
FS1 – FS4
TG1 – TG2
TM1 – TM7
PS1 – PS4
TGH
TGL
BALH
BALL
ATSC
DFCT
TM1
TG1
FS2
IFB1 – IFB6
VCC
VEE
VCC
VEE
VEE
PD 2
I-V AMP
FOK
CC2
CC1
CB
CP
RF O
RF I
RFTC
PD2
PD1
PD
LD
RF M
TA
O
TA
M
FSET
TG2
TGU
SRCH
FEO
FEI
FDFCT
FGD
FLB
FE O
FE M
TZC
FZC
FOL
FOH
MIRR
LDON
LPCL
LPC
TGFL
DFCT1
CC1
1
2
3
4
5
6
7
8
9
10
26
25
24
23
22
21
21
20
19
18
17
16
15
14
40
41
42
43
44
45
46
47
48
49
50
51
52
39
PD 1
I-V AMP
38
PD
AMP
37
LD
AMP
LASER
POWER
CONTROL
FOCUS BIAS
WINDOW
COMPARATOR
FOCUS ERROR
AMP
F I-V
AMP
AMP
E I-V
AMP
AMP
TGFL
TRACKING GAIN
WINDOW
COMPARATOR
E-F BALANCE
WINDOW
COMPARATOR
ATSC
WINDOW
COMPARATOR
TZC
COMPARATOR
TRACKING PHASE
COMPENSATION
CENTER
VOLTAGE
GENERATOR
FZC
COMPARATOR
FOCUS PHASE
COMPENSATION
CHARGE UP
FSET
ISET
IIC DATA REGISTER, INPUT SHIFT REGISTER,
ADDRESS DECODER, SENSE SELECTOR,
OUTPUT DECODER
TTL
↓
IIL
IIL
↓
TTL
IIL
↓
TTL
RF SUMMING
AMP
FOCUS OK
COMPARATOR
PEAK/BOTTOM
HOLD
PEAK/BOTTOM
HOLD
DEFECT
AMP
MIRR
COMPARATOR
36
34
31 30
29
28
27
35
33 32
BAL1 – BAL4
TM6
TM2
VCC
VEE
TM5
11
12
13
TG2
TM4
VCC
VEE
TM3
FS1
VCC
VEE
TOG1 – TOG4
TM7
FS4
DFCT
+
–
+
–
– 42 –
IC52
BA6287F-T1
– MAIN Board –
IC101
CXD2530Q
1
2
3
4
OUT1
VM
VCC
FIN
8
7
6
5
GND
OUT2
VREF
RIN
CONTROL LOGIC
TSD
POWER
SAVE
DRIVER
DRIVER
1 2 3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
43
42
42
41
40
40
39
38
38
37
36
35
34
33
32
31
31
50
49
49
48
47
47
46
45
44
88
89
89
90
91
91
92
93
93
94
95
96
97
98
99
100
81
82
82
83
84
84
85
86
87
71 70 69 68
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
80 79 78 77 76 75 74 73 72
ASYMMETRY
CORRECTOR
DIGITAL
PLL
CLOCK
GENERATOR
D / A
INTERFACE
DIGITAL CLV
SUB CODE
PROCESSOR
TIMING
LOGIC
CPU
INTERFACE
SERVO
AUTO
SEQUENCER
ERROR
CORRECTOR
16K RAM
DIGITAL OUT
OSC
EFM
DEMODULATOR
TES6
VDD
VSS
EXCK
SBSO
SCOR
WFCK
TES5
EMPH
DOUT
C4M
FSTT
XTSL
MNT0
MNT1
MNT3
XROF
C2PO
RFCK
GFS
XPCK
XUGF
GTOP
VDD
VSS
TES4
BCK
TES3
PCMD
TES9
LRCK
WDCK
ASYE
ASYO
ASYI
ASYI
BIAS
RF
AVDD
CLTV
AVSS
FILI
FILO
PCO
PCO
VCTL
V16M
VCKI
VPCO1
VPCO2
TES1
TES0
LOCK
PWMI
MDP
MDS
VSS
MON
FOK
VDD
SPOD
XLON
SPOB
SPOC
CLKO
SPOA
DATO
XLTO
SEIN
CNIN
XLAT
CLOK
SENS
DATA
SQCK
SQSO
TES2
CKOUT
LMUT
RMUT
VDD
VSS
NC
XRST
VSS
NC
NC
VDD
NC
TES8
XVSS
VSS
XTAI
XTAO
VSS
XVDD
TES7
NC
VDD
NC
NC
VSS
– 43 –
IC301
BA6287F-T1
IC302
BA8272F-E2
IC502
KM62256DLG-7LT
IC601
TC9464FN-EL
1
2
3
4
OUT1
VM
VCC
FIN
8
7
6
5
GND
OUT2
VREF
RIN
CONTROL LOGIC
TSD
POWER
SAVE
DRIVER
DRIVER
1
2
3
4
5
6
7
8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DATA OUT
DATA IN
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON IN
BUS ON OUT
RESET
RESET
SWITCH
MEMORY
MATRIX
512X512
ROW
DECODER
BUFFER
1
A14
2
3
4
5
A5
A12
A7
A6
26 A13
25 A8
24
25 A8
24
23 A11
A9
I/O GATE
COLUMN
COLUMN
DECODER
BUFFER
6
A4
7
8
9
10
A0
A3
A2
A1
27
28 VCC
WE
22 OE
21 A10
BUFFER
18 I/O7
17 I/O6
16
17 I/O6
16
I/O4
I/O5
19 I/O8
15
I/O BUFFER
11
12
13
I/O3
I/O1
I/O2
20 CE
14
GND
LEVEL
SHIFT
LEVEL
SHIFT
LEVEL
SHIFT
DIGITAL FILTER CIRCUIT
ATTENUATOR OPERATIONAL CIRCUIT
DEEMPHASIS FILTER CIRCUIT
D-
∆
MODULATION CIRCUIT
INTERFACE
CIRCUIT
TEST
CIRCUIT
OUTPUT
CIRCUIT
CIRCUIT
ANALOG
FILTER
TIMING
GENERATOR
OSC
MICROCOMPUTER
INTERFACE
CIRCUIT
OUTPUT
CIRCUIT
CIRCUIT
ANALOG
FILTER
1
2
3 4
5
6
7
8
9
10
20
19
18
17
16
15
14 13
12
11
21
22
23
24
LRCK
BCK
DATA
HS
(SM)
ATT
(EMP)
SH
(BS)
LA
VDX
XO
XI
GNDX
MCK
VDD
T1
P/S
VDA
RO
GNDA
VR
GNDA
LO
GNDD
ZD
VDA
– 44 –
7-12.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC201 CXP84332-210Q (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Function
1 to 3
—
O
Not used (open)
4
CH.F
O
Motor drive signal (load chucking direction) output to the chucking motor drive (IC52)
“L” active *1
“L” active *1
5
CH.R
O
Motor drive signal (save direction) output to the chucking motor drive (IC52)
“L” active *1
“L” active *1
6
LOAD2
I
Chucking end detect switch (SW11) input terminal
“L”: When completion of the disc chucking operation
“L”: When completion of the disc chucking operation
7
LOAD1
I
Save end detect switch (SW12) input terminal
“L”: When completion of the disc chucking operation
“L”: When completion of the disc chucking operation
8
SENS2
I
Internal status signal (sense signal) input from the CXA1992BR (IC11)
9
LIM.SW
I
Sled limit in detect switch (SW1) input terminal
“L”: When the optical pick-up is inner position
“L”: When the optical pick-up is inner position
10
EE.INIT
I
Initialize signal input for the EEPROM “H”: format Fixed at “L” in this set
11
EE.CLK
O
Serial data transfer clock signal output terminal Not used (open)
12
EE.DATA
I/O
Two-way data bus with the EEPROM Not used (open)
13 to 19
—
O
Not used (open)
20
SINGLE
I
Setting terminal for the single disc/multiple discs mode
“L”: single mode, “H”: multiple discs mode (fixed at “H”)
“L”: single mode, “H”: multiple discs mode (fixed at “H”)
21
XRST
O
System reset signal output to the CXA1992BR (IC11) and CXD2530Q (IC101) “L”: reset
22
FOK
I
Focus OK signal input from the CXA1992BR (IC11) “L”: NG, “H”: OK
23
SENS
I
Internal status signal (sense signal) input from the CXD2530Q (IC101)
24
GFS
I
Guard frame sync signal input from the CXD2530Q (IC101) “L”: NG, “H”: OK
25
GRSRT
O
Reset signal output terminal “L”: reset Not used (open)
26
XQOK
O
Subcode Q OK pulse signal output terminal “L” active Not used (open)
27
SDTI
I
ESP status signal input terminal Not used (open)
28
XSOE
O
ESP status read enable signal output terminal “L” active Not used (open)
29
ESPXLT
O
ESP latch pulse signal output terminal “L” active Not used (open)
30
RST
I
System reset signal input from the SONY bus interface (IC302) and reset signal generator (IC304)
“L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
“L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
31
EXTAL
I
Main system clock input terminal (8 MHz)
32
XTAL
O
Main system clock output terminal (8 MHz)
33
VSS
—
Ground terminal
34
TX
O
Sub system clock output terminal Not used (open)
35
TEX
I
Sub system clock input terminal Not used (fixed at “L”)
36
AVSS
—
Ground terminal (for A/D converter)
37
AVREF
I
Reference voltage (+5V) input terminal (for A/D converter)
38
MCK
I
Input of signal for the fine adjustment (linear position sensor adjustment; RV201) of elevator
position (A/D input)
position (A/D input)
39
EHS
I
Elevator height position detect input from the RV202 (elevator height sensor) (A/D input)
40
MODEL
I
Setting terminal for the destination (fixed at “L” in this set)
41
XRDE
O
D-RAM read enable signal output terminal “L” active Not used (open)
42
XWRE
O
D-RAM write enable signal output terminal “L” active Not used (open)
43
A.MUTE
O
Audio line muting on/off control signal output terminal “H”: muting on
44
EMP
O
Emphasis mode output to the D/A converter (IC601) “H”: emphasis on
45
ML
O
Fast speed dubbing control signal output to the D/A converter (IC601) “L”: fast speed
46
GRSCOR
I
Subcode sync (S0+S1) detection signal input terminal Not used (open)
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