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28

1
2

3

4

5

6

7

8

9

10

VCC

IN2

S-GND

IN1

NC

NC

OUT2

NC

P-GND

OUT1

CONTROL

CIRCUIT

MOTOR

DRIVE

CIRCUIT

BUFFER

BUFFER

2

VOUT

3

GND

1

VIN

4

CONT

CONTROL

DEVICE

ADDRESS

COMPARATOR

Y DEC

H.V. PUMP/TIMING

DATA RECOVERY

E

2

PROM

SERIAL MUX

START

STOP

LOGIC

SERIAL

CONTROL

LOGIC

DATA WORD

ADDR/COUNTER

D

OUT

/ACK

LOGIC

1
2

3

4

5

6

7

8

X DEC

VCC

TST

SDL

SDA

A0

A1
A2

GND

COMP

LOAD

LOAD INC

R/W

EN

D

OUT

D

IN

1

2

3

4

5

6

7

8

9

10

14

13

12

11

VCC

BUS ON

LINK OFF

CLK OUT

DATA OUT

DATA IN

BUS RESET

BUS DATA

VREF

BUS CLK

GND

BUS ON IN

BUS ON OUT

RESET

RESET

SWITCH

29

• 

Pin No.

Pin Name

I/O

Description

1

ESPSEL

I

ESP on/off setting terminal    “L”: ESP on    Not used (open)

2

ML

O

Normal/high speed playback control signal output terminal    “L”: high speed playback
Not used (open)

3

EMPHO

O

Emphasis signal output terminal    Not used (open)

4

AMUTE

O

Audio line muting on/off control signal output terminal    “H”: muting on

5

CDXLT

O

Serial data latch pulse signal output to the CXD2598Q (IC101)

6

CDDATA

O

Serial data output to the CXD2598Q (IC101)

7

CDCLK

O

Serial data transfer clock signal output to the CXD2598Q (IC101)

8

CDON

O

D/A converter and servo section power supply on/off control signal output    “H”: power on

9

ELVON

O

Mechanism deck section power supply on/off control signal output    “H”: power on

10

DOUTSEL

I

Digital output on/off control signal input terminal     “L”: digital output on    Not used (open)

11

NC

—

Not used (open)

12

RAMWE

O

Data write enable signal output to the S-RAM (IC202) (CDX-636 only)     “L”: active
CDX-601: Not used (open)

13 to 20

RAMIO8 to RAMIO1

I/O

Two-way data bus with the S-RAM (IC202) (CDX-636 only)     CDX-601: Not used (open)

21 to 28

RAM7 to RAM0

O

Address signal output to the S-RAM (IC202) (CDX-636 only)     CDX-601: Not used (open)

29

NC

—

Not used (open)

30 to 36

RAM14 to RAM8

O

Address signal output to the S-RAM (IC202) (CDX-636 only)     CDX-601: Not used (open)

37

RAMCE

O

Chip enable signal output to the S-RAM (IC202) (CDX-636 only)     “L”: active
CDX-601: Not used (open)

38

RESET

I

System reset signal input from the SONY bus interface (IC302) and reset signal generator (IC303)
“L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”

39

GND

—

Ground terminal

40

XTAL

O

Main system clock output terminal (12 MHz)

41

EXTAL

I

Main system clock input terminal (12 MHz)

42

TEXTSEL

I

CD text mode setting terminal    “L”: CD text on, “H”: does not display track name
CDX-601: fixed at “H” (open)    CDX-636: fixed at “L”

43

SI

I

Serial data input from the SONY bus interface (IC302)

44

SO

O

Serial data output to the SONY bus interface (IC302)

45

SCLK

I

Serial data transfer clock signal input from the SONY bus interface (IC302)

46

CFSEL

I

Custom file on/off setting terminal    “L” custom file on
CDX-601: fixed at “H” (open)    CDX-636: fixed at “L”

47

EEINIT

I

Initialize signal input for the EEPROM (IC203)    “H”: format
CDX-601: not used (open)    CDX-636: fixed at “L”

48

EEDATA

I/O

Two-way data bus with the EEPROM (IC203) (CDX-636 only)    CDX-601: not used (open)

49

EECLK

O

Serial data transfer clock signal output to the EEPROM (IC203) (CDX-636 only)
CDX-601: not used (open)

50

VSS

—

Ground terminal (for A/D converter)

51

AVREF

I

Reference voltage (+5V) input terminal (for A/D converter)

52

VDD

—

Power supply terminal (+5V) (for A/D converter)

53

SINGLE

I

Setting terminal for the single disc/multiple discs mode
“L”: single mode, “H”: multiple discs mode    Fixed at “H” in this set (open)

54

LDON

O

The laser automatic power control on/off signal output    “H”: automatic power control on

55

AGCHOLD

O

RF AGC hold on/off signal output    “H”: hold

56

RFAGC

I/O

RF AGC level control signal output    “L”: off, center voltage: 40%, “H”: 60%

30

Pin No.

Pin Name

I/O

Description

57, 58

AD

I

A/D input terminal

59

EHS

I

Elevator height position detect input from the RV202 (elevator height sensor) (A/D input)

60

MCK

I

Input of signal for the fine adjustment (elvator height (address) adjustment; RV201) of elevator
position (A/D input)

61

NC

—

Not used (open)

62

BUSON

I

Bus on/off control signal input from the SONY bus interface (IC302)    “H” bus on

63

EJECT

I

Eject switch (SW801) input terminal    “H” active

64

MAGSW

I

Magazine in/out detect switch input    Not used (open)

65

LOAD1

I

Chucking end detect switch (SW1) input terminal
“L”: When completion of the disc chucking operation

66

LOAD2

I

Save end detect switch (SW2) input terminal
“L”: When completion of the disc save operation

67 to 70

NC

—

Not used (open)

71

CH.F

O

Motor drive signal (save direction) output to the chucking motor drive (IC201)
“L” active    *1

72

CH.R

O

Motor drive signal (chucking direction) output to the chucking motor drive (IC201)
“L” active    *1

73

ELVR

O

Motor drive signal (elevator down direction) output to the elevator motor drive (IC301)
“L” active    *2

74

ELVF

O

Motor drive signal (elevator up direction) output to the elevator motor drive (IC301)
“L” active    *2

75

BUCHK

I

Battery detect signal input terminal    “H”: battery on

76

MGLK

I

Magazine detect switch (SW201) input    “L”: magazine is set

77

SQSO

O

Subcode Q/text serial data output to the CXD2598Q (IC101)

78

NC

—

Not used (open)

79

SQCK

O

Subcode Q/text serial data transfer clock signal output to the CXD2598Q (IC101)

80

GRSCOR

I

Subcode sync (S0+S1) detection signal input terminal    Not used (open)

81

NC

—

Not used (open)

82

SCOR

I

Subcode sync (S0+S1) detection signal input from the CXD2598Q (IC101)

83

SIRCS

I

SIRCS signal input terminal    Not used (open)

84

TEX

I

Sub system clock input terminal    Not used (open)

85

TX

O

Sub system clock output terminal    Not used (open)

86

VSS

—

Ground terminal

87

VDD

—

Power supply terminal (+5V)

88

NC

—

Not used (open)

89

LIMSW

I

Sled limit in detect switch (SW3) input terminal
“L”: When the optical pick-up is inner position

90

FOK

I

Focus OK signal input from the CXD2598Q (IC101)    “H” is input when focus is on (“L”: NG)

91

GFS

I

Guard frame sync signal input from the CXD2598Q (IC101)    “L”: NG, “H”: OK

92

SCLK

O

Serial data transfer clock signal output to the CXD2598Q (IC101)

93

SENS

I

Internal status signal (sense signal) input from the CXD2598Q (IC101)

94

XRST

O

System reset signal output to the CXD2598Q (IC101)    “L”: reset

95

NC

—

Not used (open)

96

ESPXQOK

O

Subcode Q OK pulse signal output terminal    “L”: active    Not used (open)

97

SDTO

I

ESP status signal input terminal    Not used (open)

98

XSOE

O

ESP status read enable signal output terminal    “L”: active    Not used (open)

99

ESPXRED

O

ESP read enable signal output terminal    “L”: active    Not used (open)

100

ESPXWRE

O

ESP write enable signal output terminal    “L”: active    Not used (open)

31

*1  chucking motor (M103) control

STOP

LOAD

CHUCKING

SAVE

BRAKE

CH.F (pin ua)

“H”

“H”

“L”

“L”

CH.R (pin us)

“H”

“L”

“H”

“L”

Mode

Terminal

*2  elevator motor (M104) control

STOP

ELEVATOR 

UP

ELEVATOR

DOWN

BRAKE

ELVF (pin uf)

“H”

“L”

“H”

“L”

ELVR (pin ud)

“H”

“H”

“L”

“L”

Mode

Terminal