DOWNLOAD Sony CDX-4483ESP Service Manual ↓ Size: 1.24 MB | Pages: 51 in PDF or view online for FREE

Model
CDX-4483ESP
Pages
51
Size
1.24 MB
Type
PDF
Document
Service Manual
Brand
Device
Car Audio
File
cdx-4483esp.pdf
Date

Sony CDX-4483ESP Service Manual ▷ View online

– 21 –
AM RF signal
generator
AM dummy
antenna (50 
)
set
antenna
terminal
30 
15 pF
65 pF
MW Auto Scan/Stop Level Adjustment
Setting :
D-BASS switch
: OFF
SOURCE 
n MODE button : MW
Carrier frequency : 999 kHz
30% amplitude
modulation by
1 kHz signal
output level
: 33 dB (44.7 
µ
V)
Procedure :
1. Set to the test mode. (See page 19.)
2. Push the  SOURCE  button.
3. Push the  MODE  button and set to MW.
Display
4. Push the preset  3  button.
Display
5. Adjust with the volume RV1 on TU1 so that the “MW”
indication turns to “MW0” indication on the display window.
But, in case of already indicated “MW0”, turn the RV1 so that
put out light “0” indication and adjustment.
Display
Adjustment Location : See page 22.
TP
SHUF
TP
SHUF
TP
SHUF
Carrier frequency : 69.5 MHz (FM2 : 3CH)
Output level
: 60 dB (1 mV)
Procedure :
1. Connect the level meter to the TP1 on main board.
2. Set the modulation frequency of the FM RF signal generator to
1 kHz (10 kHz div.).
3. Then output level is supposing that 0 dB.
4. Set the modulation frequency of the FM RF signal generator to
31.25 kHz (10 kHz div.).
5. Adjust L604 so that the reading on the level meter becomes to
maximum.
6. Adjust RV602 so that the reading on the level meter becomes to
13.0 
±
 0.5 dB.
Adjustment Location : See page 22.
FM Polar Pilot Adjustment
Setting :
D-BASS switch : OFF
SOURCE button : FM
FM RF signal
generator
antenna
terminal
set
+
level meter
main board
TP1
– 22 –
Adjustment Location : tuner unit (TU1)
TU1
– set upper view –
RV1
MW AUTO SCAN/
STOP LEVEL ADJ
RV2
FM AUTO SCAN/
STOP LEVEL ADJ
RV4
FM STEREO
SEPARATION ADJ
RV601
FM POLAR 
VCO ADJ
L604    RV602
FM POLAR 
PILOT ADJ
TP1
FM POLAR
PILOT ADJ
TP2
FM POLAR
VCO ADJ
IC601
– main board (side B) –
– 23 –
4-1. IC PIN DESCRIPTIONS
• IC5 CXP84640-003Q (CD SYSTEM CONTROL)
Pin No.
Pin Name
I/O
Pin Description
1 – 7
NCO
Not used in this set.
8
LINKOFF
I
Bus interface link input (Not used in this set.)
9
DRV OE
O
Focus/tracking coil/sled motor control output
10
D SW
I
Down switch input (SW4)
11 – 13
NCO
Not used in this set.
14
LM EJ
O
Loading motor control output
15
LM LOD
O
Loading motor control output
16
EMPH O
O
De-emphasis ON/OFF control output
17
CDMON
O
CD mechanism deck power control output
18
CD ON
O
CD power control output
19
A MUT
O
System attenuate control output
20
LD ON
O
Lazer power ON/OFF control output
21
CD RST
O
CD system reset output
22 – 24
Not used in this set.
25
PH3
I
Not used in this set.
26
TSTIN0
I
Not used in this set.
27
TSTIN1
I
Not used in this set.
28
TST CLV
I
Not used in this set.
29
NCO
Not used in this set.
30
RESET
I
System reset input (“L” = Reset)
31
X IN
I
X’tal oscillator input of system clock. (10 MHz)
32
X OUT
O
X’tal oscillator output of system clock. (10 MHz)
33
GND
Analog GND
34
XT OUT
O
Not used in this set.
35
XT IN
I
Not used in this set.
36
AVSS
A/D converter GND
37
AVREF
I
A/D converter reference voltage input
38
TEP L
I
Not used in this set.
39
TEP H
I
Not used in this set.
40
NCO
Not used in this set.
41
PH2
I
Not used in this set.
42
SCLK
O
CD-TEXT data read clock output
43
ESPXQOK
O
XQOK signal output to DRAM controller.
44
ESPSDT
I
Serial data input from DRAM controller.
45
GRSRST
O
Reaet signal output to DRAM controller.
46
GRSCOR
I
Sub-cord sync input from DRAM controller.
47
CD XLAT
O
CD signal process serial latch output
48
TX CLK
O
EEPROM serial clock output (Not used in this set.)
49
TX DATA
O
EEPROM serial data output (Not used in this set.)
50
UNISO
O
Not used in this set.
51
BUS CLK
I/O
Bus system serial clock input/output
52
BUS SI
I
Bus system serial interface input
53
BUS SO
O
Bus system serial interface output
54
F OK
I
Focus OK signal input
55
GFS
I
GFS signal detection input
56
SCOR
O
Sub-cord sync output
57
SENS
I
SENS signal input
58
I
Fixed at “H” in this set.
59
CD CKO
O
CD signal process serial clock output
60
BU.IN
I
Back-up power detection input
61
BUSON
I
Bus on control input
SECTION 4
DIAGRAMS
– 24 –
Pin No.
Pin Name
I/O
Pin Description
62
IN SW
I
Disc in switch input (SW1)
63
SELF SW
I
Self switch input (SW2)
64
TX CE
O
EEPROM chip enable output (Not used in this set.)
65
SCK2
O
Sub Q read clock output
66
SI2
I
Sub Q 80 bit, PCM peak and level data 16 bit input
67
CD DATA
O
CD signal process serial data output
68
ESPXWRE
O
Write signal output to DRAM controller.
69
ESPXRDE
O
Read signal output to DRAM controller.
70
ESPXLT
O
Serial data latch output to DRAM controller.
71
ESPXSOE
O
XSOE signal output to DRAM controller.
72
VDD
Power supply
73
HIN
I
Fixed at “H” in this set.
74
TEXT.ON/OFF
I
Fixed at “H” in this set.
75
PH1
I
Not used in this set.
76
FBTBSEL
I
Not used in this set.
77
CDOSEL
I
Not used in this set.
78 – 80
Not used in this set.
Page of 51
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