Sony ZS-YN7L Service Manual ▷ View online
37
ZS-YN7L
•
IC Pin Function Description
CD BOARD IC702 CXD3029R (CD DSP)
Pin No.
Pin Name
I/O
Description
1
XRAS
O
Row address strobe signal output to the D-RAM
2
XWE
O
Data input enable signal output to the D-RAM
3 to 6
D1, D0, D3, D2
I/O
Two-way data bus with the D-RAM
7, 8
TEST1, TEST2
O
Not used
9
XCAS
O
Column address strobe signal output to the D-RAM
10
WFCK
O
Not used
11 to 13
A9 to A7
O
Address signal output to the D-RAM
14
DVSS
—
Ground terminal
15 to 17
A6 to A4
O
Address signal output to the D-RAM
18
XRDE
I
Read enable signal input from the MP3 decoder
19
VDD0
—
Power supply terminal (+3.3V)
20
CLOK
I
Serial data transfer clock signal input from the system controller
21
DATA
I
Serial data input from the system controller
22
SENS
O
SENS signal output to the system controller
23
XLAT
I
Serial data latch pulse signal input from the system controller
24
XSOE
I
Serial data output enable signal input from the system controller
25
SYSM
I
Analog muting on/off control signal input from the system controller “H”: muting on
fixed at “L” in this set
fixed at “L” in this set
26
WDCK
O
Not used
27
SCOR
O
Subcode sync (S0+S1) detection signal output to the system controller
28
XRST
I
Reset signal input from the system controller “L”: reset
29
PWMI
I
Not used
30
XQOK
I
Not used
31
XWRE
I
Not used
32
R8M
O
System clock output terminal Not used
33
VSS0
—
Ground terminal
34
SQCK
I
SQSO readout clock signal input terminal Not used
35
SCLK
I
SENS serial data read clock signal input terminal Not used
36
SQSO
O
Not used
37
XEMP
O
Not used
38
XWIH
O
Not used
39
SBSO
O
Not used
40
EXCK
O
SQSO readout clock signal output terminal Not used
41
XTSL
I
Input terminal for the system clock frequency setting fixed at “L” in this set
42
HVSS
—
Ground terminal
43
HPL
O
Not used
44
HPR
O
Not used
45
HPVDD
—
Power supply terminal (+3.3V)
46
XVDD
—
Power supply terminal (+3.3V)
47
XTAI
I
System clock input terminal (16.9344 MHz)
48
XTAO
O
System clock output terminal (16.9344 MHz)
49
XVSS
—
Ground terminal
50
AVDD1
—
Power supply terminal (+3.3V)
51
AOUT1
O
L-ch analog audio signal output terminal
52
VREFL
O
L-ch reference voltage output terminal
38
ZS-YN7L
Pin No.
Pin Name
I/O
Description
53, 54
AVSS1, AVSS2
—
Ground terminal
55
VREFR
O
R-ch reference voltage output terminal
56
AOUT2
O
R-ch analog audio signal output terminal
57
AVDD2
—
Power supply terminal (+3.3V)
58
TES1
I
Input terminal for the test (fixed at “L”)
59
TEST
I
Input terminal for the test (fixed at “L”)
60
VSS1
—
Ground terminal
61
LRMU
O
Muting on/off control signal output terminal Not used
62
DOUT
O
Digital audio signal output terminal when playback mode
63
ATSK
I/O
Not used
64
DFCT
I/O
Not used
65
FOK
O
Focus OK signal output to the system controller
66
MIRR
I/O
Not used
67
COUT
I/O
Not used
68
C2PO/MNT3/
GTOP
O
Not used
69
GFS/MNT2/
XROF
O
GFS signal output to the system controller
70
XUGF/MNT0/
RFCK
O
Not used
71
XPCK/MNT1/
XPCK
O
Not used
72
VDD1
—
Power supply terminal (+3.3V)
73
PCO
O
Charge pump output terminal for master PLL
74
FILI
I
Filter input terminal for master PLL
75
FILO
O
Filter output terminal for master PLL
76
CLTV
I
VCO1 control voltage input terminal for multiplier
77
VCTL
I
VCO2 control voltage input terminal for broad-band EFM PLL
78
VPCO
O
Charge pump output terminal for broad-band EFM PLL
79
AVSS3
—
Ground terminal
80
ASYO
O
EFM full-swing output terminal
81
ASYI
I
Asymmetry comparator voltage input terminal
82
BIAS
I
Asymmetry circuit constant current input terminal
83
AVDD3
—
Power supply terminal (+3.3V)
84
RFAC
I
EFM signal input from the RF amplifier
85
AVDD0
—
Power supply terminal (+3.3V)
86
IGEN
I
Stabilized current input terminal
87
AVSS0
—
Ground terminal
88
RFDC
I
RF signal input from the RF amplifier
89
CE
I
Chip enable signal input terminal Not used
90
TE
I
Tracking error signal input from the RF amplifier
91
SE
I
Sled error signal input from the RF amplifier
92
FE
I
Focus error signal input from the RF amplifier
93
VC
I
Middle point voltage input terminal
94
VSS2
—
Ground terminal
95
FRDR
O
Focus servo drive signal (–) output to the coil/motor drive
96
FFDR
O
Focus setvo drive signal (+) output to the coil/motor drive
39
ZS-YN7L
Pin No.
Pin Name
I/O
Description
97
TRDR
O
Tracking servo drive signal (–) output to the coil/motor drive
98
TFDR
O
Tracking servo drive signal (+) output to the coil/motor drive
99
SRDR
O
Sled servo drive signal (–) output to the coil/motor drive
100
SFDR
O
Sled servo drive signal (+) output to the coil/motor drive
101
SSTP
I
Disc inner position detection signal input terminal
102
MDS
O
Spindle motor drive signal output terminal Not used
103
MDP
O
Spindle motor servo control signal output to the coil/motor drive
104
C176
O
176.4 kHz clock signal output terminal Not used
105
VDD2
—
Power supply terminal (+3.3V)
106
LRCK
O
L/R sampling clock signal output to the MP3 decoder
107
LRCKI
I
L/R sampling clock signal input from the MP3 decoder
108
PCMD
O
Serial data output to the MP3 decoder
109
PCMDi
I
Serial data input from the MP3 decoder
110
BCK
O
Bit clock signal output to the MP3 decoder
111
BCKI
I
Bit clock signal input from the MP3 decoder
112
DVDD
—
Power supply terminal (+3.3V)
113 to
117
A3 to A0, A10
O
Address signal output to the D-RAM
118
A11
O
Not used
119, 120
TEST3, TEST4
O
Not used
40
ZS-YN7L
MAIN BOARD IC802 TMP91CY22FG-5HF7 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
VREFL
I
Reference voltage input terminal (0V)
2
AVSS
—
Ground terminal
3
AVCC
—
Power supply terminal (+3.3V)
4
RW/ROM
O
CD-ROM/RW or LD on/off selection signal output terminal
5
PWM RF
O
RF offset cancel PWM signal output terminal
6
PWM TE
O
Tracking error offset cancel PWM signal output terminal
7
EEP CSO
O
Chip select signsl output terminal Not used
8
PWM FE
O
Focus error offset cancel PWM signal output terminal
9
LD ON
O
Laser diode on/off control signal output to the automatic power control circuit
“H”: laser diode on
“H”: laser diode on
10
K-SEL
O
DNK selection signal input terminal Not used
11
3.3V REG
I
CD voltage detection signal input terminal
12
XRSTO
O
System reset signal output to the CD DSP “L”: reset
13
FOKI
I
Focus OK signal input from the CD DSP “L”: NG, “H”: OK
14
SCORI
I
Subcode sync (S0+S1) detection signal input from the CD DSP
15
GFSI
I
Guard frame sync signal input from the CD DSP “L”: NG, “H”: OK
16
XLATO
O
Serial data latch pulse output to the CD DSP
17
XSOEO
O
Serial data output enable signal output to CD DSP
18
DATAO
O
Serial data output to the CD DSP
19
SENSIN
I
Internal status (SENSE) signal input from the CD DSP
20
CLKO
O
Serial data transfer clock signal output to the CD DSP
21
R-DATA
O
PLL serial data output terminal
22
R-COUNT
I
PLL serial data input terminal
23
R-CLOCK
O
PLL serial data transfer clock signal output terminal
24
AMO
O
Not used
25
DVCC
—
Power supply terminal (+3.3V)
26
X2
O
System clock output terminal (4.19 MHz)
27
DVSS
—
Ground terminal
28
X1
I
System clock input terminal (4.19 MHz)
29
AMI
I
Not used
30
RESET
I
System reset signal input from the reset signal generator “L”: reset
31
SHIFT1
O
Shift point terminal for oscillation frequency change
32
NC
O
Not used
33, 34
EMU0, EMU1
O
Not used
35
WP
I
Key interruption processing start signal input terminal
36
AC-IN
O
AC power detection input terminal “L”: AC power on
37
CD DOOR
I
CD lid open/close detection switch input terminal “L”: CD lid is close
38
REMOTE
I
Remote control signal input terminal
39
R-MUTE
O
Tuner muting on/off control signal output terminal “H”: active
40
R-CE
O
PLL chip enable signal output terminal
41
EEP-SDA
I/O
Two-way serial data bus with the EEPROM
42
EEP-SCL
O
Serial clock signal output terminal to the EEPROM
43
ALE
O
Not used
44 to 51
LCD-AD0 to
LCD-AD7
O
LCD serial data output terminal
Click on the first or last page to see other ZS-YN7L service manuals if exist.