Sony ZS-SN10 Service Manual ▷ View online
25
25
ZS-SN10
ZS-SN10
5-13. SCHEMATIC DIAGRAM – PANEL SECTION –
R437
R427
R417
C401
R492
R490
R491
C407
C408
C409
C410
C411
C412
C413
C414
C417
C418
C404
C403
C402
C406
R415
R416
R458
C420
R494
R493
R438
R439
R436
R454
R453
S424
R452
S422
R450
R449
R448
R447
R446
CN405
R432
R431
R430
S405
R429
S404
R428
CN404
R425
R421
R420
R418
R419
S403
R426
S402
IC401
R401
C419
CN403
R440
R451
LCD401
L401
47
47
µH
L403
L402
R459
D402
S401
CN402
R402
S423
S418
S419
S420
S421
S411
S412
S413
S414
S425
CN401
D401
S407
S406
C405
S410
470
470
470k
1
10k
2.2k
0
47p
47p
47p
47p
47p
47p
47p
47p
47p
47p
1
1
1
0.01
47k
100k
470
0.01
2.2k
1k
1k
1k
220
4.7k
2.2k
1k
2.2k
1k
1k
470
220
11P
2.2k
1k
2.2k
1k
1k
2P
220
1k
1k
470
470
220
RPM7140
1k
0.01
4P
2.2k
2.2k
11P
1k
2P
L-34HD
470p
*
*
SW 9V
KEY0
D-GND2
D-GND2
*R459
220
470
(WHITE:US,CND)
(EXCEPT WHITE:US,CND)
(WHITE:US,CND)
(EXCEPT WHITE:US,CND)
*D402
SLI-343YC3F
SLR343EBT
(LCD BACK LIGHT)
B
GND
A
ROTARY ENCODER(JOG)
DISPLAY
MODE
PRESET –
PRESET +
LINE
/TUNE
+
/TUNE
–
ENTER/
MEMORY
POWER
SLEEP
OPR/BATT
KEY0
SOUND
MEGA BASS
VOLUME
–
VOLUME
+
KEY0
D-GND2
SEARCH
REPEAT
RADIO/BAND
AUTO
PRESET
D-GND2
1
µH
1
µH
(Page 22)
(Page 22)
(Page 22)
Ver. 1.3
26
26
ZS-SN10
ZS-SN10
•
Waveforms
– CD Board –
IC402 FAN8040G3
•
IC Block Diagrams
– CD Board –
ws
IC801
id
(X1)
1 V/DIV, 100 ns/DIV
239 ns
3.7 Vp-p
qa
IC2
w;
(XOUT)
500 mV/DIV, 5
µ
s/DIV
13.3
µ
s
0.9 Vp-p
wa
IC801
ul
(X1A)
1 V/DIV, 10
µ
s/DIV
30.5
µ
s
3.5 Vp-p
3
IC201
u;
(RFACO)
(CD PLAY mode)
200 mV/DIV, 500 ns/DIV
0.5 to 1.1 Vp-p
22.8
µ
s
3.3 Vp-p
1
IC201
1
(LRCK)
(CD PLAY mode)
1 V/DIV, 10
µ
s/DIV
2
IC201
5
(BCK)
(CD PLAY mode)
1 V/DIV, 200 ns/DIV
472 ns
3.3 Vp-p
4
IC201
<z/,
(XTAO)
(CD PLAY mode)
1 V/DIV, 20 ns/DIV
59.4 ns
2.3 Vp-p
– TUNER Board –
– MAIN Board –
IC1 TA2149BN
– TUNER Board –
1
LEVEL SHIFT
MUTING
D
15
16
+ –
+
–
D
D
17
18
D
19
20
VREF
21
22
23
24
25
26
27
28
PREVCC
OPOUT
OUTVREF
CH4CAPA
CH4IN
CH3FIN
CH3RIN
GND
MUTE
POWVCC
CH3OUTF
CH3OUTR
CH4OUTF
CH4OUTR
OPIN–
2
OPIN+
INTERFACE
14
13
D
12
11
D
10
9
8
7
6
CH2FIN
CH2RIN
GND
5
4
CH1FIN
CH1RIN
VREFIN
POWVCC
CH2OUTR
CH2OUTF
CH1OUTR
CH1OUTF
INTERFACE
D
D
3
SW
INTERFACE
RF GND
3
2
1
IF REQ
AM
MIX
FM RFIN
AM LOW CUT
5
4
MIX OUT
VCC
AM IF IN
8
7
6
FM IF IN
GND
10
9
AGC
QUAD
12
11
R-OUT
L-OUT
FM RFOUT
22
23
24
20
21
17
18
19
15
16
13
14
AM RFIN
RF VCC
FM OSC
ST LED
OSC OUT
AM OSC
IF REQ
LPF1
MPX IN
DET OUT
LPF2
FM
MIX
FM
OSC
LEVEL
DET
AM
DET
MUTE
FM
DET
ST/MO
FM/AM
AM
OSC
AGC
SW
ST
1/8
BUFF
BUFF
DIVIDE
DECODE
VCO
IF BUFF
AF BUFF
AF
FM RF
AM IF
FM IF
1/1 OR
1/16
11
10
9
8
7
6
5
4
3
2
1
12
13
14
15
16
19
20
UNLOCK
DETECTOR
POWER ON
RESET
UNIVERSAL
COUNTER
CCB
I/F
CE
DI
CL
DO
XOUT
AOUT
XIN
AIN
PD
VSS
VDD
B04
FMIN
AMIN
B01
B02
B03
I01
I02
IFIN
PHASE
DETECTOR
CHARGE
PUMP
REFERENCE
DIVIDER
SWALLOW
COUNTER
1/16,1/17
4BITS
12BITS
PROGRAMMABLE
DIVIDER
DATA SHIFT REGISTER
LATCH
1/2
17
18
IC2 LC72137M-TLM-E
Ver. 1.3
27
ZS-SN10
IC301 BD3870FS-E2
– MAIN Board –
IC901 S-816A33AMC-BAI-T2-G
3
2
5
OVERCURRENT
PROTECT
CIRCUIT
REFERENCE
VOLTAGE
ERROR
AMP
SINK
DRIVER
4
1
VOUT
VIN
ON/OFF
VSS
EXT
SOURCE
POWER
SUPPLY
28
ZS-SN10
• IC Pin Function Description
CD BOARD IC201 CXD3014-201R (CD DSP)
CD BOARD IC201 CXD3014-201R (CD DSP)
Pin No.
Pin Name
I/O
Description
1
LRCK
O
L/R sampling clock signal output terminal
2
LRCKI
I
L/R sampling clock signal input terminal
3
PCMD
O
Serial data output terminal
4
PCMDI
I
Serial data input terminal
5
BCK
O
Bit clock signal output terminal
6
BCKI
I
Bit clock signal input terminal
7
XTACN
I
Oscillation circuit on/off switch control signal input from the system controller
“H”: self-oscillation, “L”: oscillation stop
8
XRST
I
Reset signal input from the system controller “L”: reset
9
VSS
—
Ground terminal
10
IREQ
I
Codec data request signal input from the system controller
11
CLOK
I
CD serial data transfer clock signal input from the system controller
12
DATA2
I/O
Codec serial data input/output with the system controller
13
XLAT2
I
Codec serial data latch pulse input from the system controller
14
REQ
I
Codec chip select signal input from the system controller
15
ACK
I
Codec acknowledge signal input from the system controller
16
XLAT
I
CD serial data latch pulse input from the system controller
17
VDD
—
Power supply terminal (+2.5V)
18
SVSS
—
Ground terminal
19
SVDD
—
Power supply terminal (+2.5V)
20
SENS
O
SENS signal output to the system controller
21
WFCK
—
Not used
22
XUGF
—
Not used
23
XPCK
—
Not used
24
GFS
—
Not used
25
C2PO
—
Not used
26
SCOR
O
Subcode sync (S0+S1) detection signal output to the system controller
27
VDD
—
Power supply terminal (+2.5V)
28
COUT
—
Not used
29
SVSS
—
Ground terminal
30
SVDD
—
Power supply terminal (+2.5V)
31
MIRR
—
Not used
32
DFCT
—
Not used
33
FOK
—
Not used
34
VSS
—
Ground terminal
35
VDD
—
Power supply terminal (+2.5V)
36
VSS
—
Ground terminal
37
MIRR
—
Not used
38
MDP
O
Spindle motor servo control signal output terminal
39
SSTP
I
Disc inner position detection signal input terminal
40
IOVSS1
—
Ground terminal
41
SFDR
O
Sled servo drive signal (+) output to the coil/motor drive
42
SRDR
O
Sled servo drive signal (–) output to the coil/motor drive
43
TFDR
O
Tracking servo drive signal (+) output to the coil/motor drive
44
TRDR
O
Tracking servo drive signal (–) output to the coil/motor drive
45
FFDR
O
Focus setvo drive signal (+) output to the coil/motor drive
46
FRDR
O
Focus servo drive signal (–) output to the coil/motor drive
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