Sony ZS-S2IP Service Manual ▷ View online
ZS-S2iP
ZS-S2iP
33
33
5-15. SCHEMATIC DIAGRAM – POWER SUPPLY Section –
J901
T901
F902
F903
C
90
1
D
90
1
D
90
2
C
90
2
D
90
4
C
90
3
D
90
3
C
90
4
C
90
6
R910
CN901
CN902
IC901
CN906
R912
R917
C913
C914
C917
C918
C905
CN905
JW908
R905
R906
R907
C912
CN903
C915
R908
Q902
D909
Q901
FH901
AEP,UK,AUS
MODEL
US,CND
MODEL
FH902
FH903
FH904
(Page 27)
(Page 27)
(Page 24)
Ver. 1.1
ZS-S2iP
ZS-S2iP
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34
• IC Block Diagrams
IC1 LV23003VA (MAIN Board (1/4))
1
AM RF-IN
3
FM MIX-OUT
2
REG
6
VCC1
4
GND1
AM
RF
AM
MIX
AM
DET
AM
IF
FM
DET
FM
IF
SD
FF
VCO
FF
FF
ST
TRIG
STSW
FM
MIX
FM
OSC
AM
OSC
OSC
BUFFER
FM
S-METER
DECODER
PHASE
COMPARATOR
MUTE
PROGRAMMABLE
DIVIDER
REFERENCE
DIVIDER
UNLOCK
DETECTOR
SWALLOW
COUNTER
POWER ON
RESET
DATA SHIFT
REGISTER
LATCH
PHASE
DETECTOE
CHARGE
PUMP
UNIVERSAL
COUNTER
5
AM MIX-OUT
7
AM IF-IN
8
FM IF-IN
9
P-DET
10
P-COMP
11
FM-DET
12
L-OUT
13
R-OUT
14
VSS
FM
RF
36 FM RF-IN
35 GND2
34 FM RF-OUT
33 VCC2
35 GND2
34 FM RF-OUT
33 VCC2
30 BO2
29 BO1
29 BO1
32 FM OSC
31 AM OSC
28 LP-OUT
27 LP-IN
27 LP-IN
23 DET-OUT
15
CE
16
DI
17
CL
18
DO
22 MPX-IN
19 X IN
20 X OUT
21 VDD
26 PD
25 AGC
25 AGC
24 AM LOW CUT
LOW-PASS
FILTER
AGC
IF
BUFFER
PIROT
DET
CCB
I/F
1
2
3
4
5
6
7
8
9
10
11
12
13
13
14
28
27
26
24
23
22
21
20
19
18
17
16
15
25
LEVEL
SHIFT
LEVEL
SHIFT
THERMAL
SHUT-DOWN
MONITOR
LEVEL
SHIFT
LEVEL
SHIFT
D.BUFF
D.BUFF
D.BUFF
GND
SLIN
(SLIN)
VREF
VCC
VCC
(FIN)
FIN
F–
F+
SL+
SL–
NC
OPIN
SP–
REG–B
SP+
SPIN
RST
REGO
MUTE
GND
TIN
(TIN)
T–
T+
GND
OPOUT
D.BUFF
D.BUFF
D.BUFF
D.BUFF
D.BUFF
REGULATOR
DRIVER
MUTE
VCC
VCC
IC703 BA5826HFP-E2 (MAIN Board (2/4))
IC805 S-24CS02AFT-TB-G (MAIN Board (3/4))
START/STOP
DETECT CIRCUIT
HIGH VOLTAGE
GENERATOR
DATA OUTPUT/
ACK OUTPUT/
CONTROL CIRCUIAT
DATA
REGISTER
EEPROM
X DECODER
SELECTOR
DEVICE
ADDRESS
COMPARATOR
SERIAL CLOCK
CONTROL CIRCUIT
ADDRESS
COUNTER
Y DECODER
LOAD
COMP
LOAD
R/W
DOUT
DIN
A0
A1
A2
GND
INC
1
2
3
4
SDA
SCL
WP
VCC
5
6
7
8
Ver. 1.1
ZS-S2iP
35
IC302 R2S15904SP (MAIN Board (4/4))
IC303 UTC8227S (MAIN Board (4/4))
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
24
23
22
21
20
19
18
17
16
15
25
VCC
IN-L3
IN-L4
A-GND
DGND
REF-IN
IN-L1
IN-R1
IN-R2
IN-R3
IN-R4
IN-L2
TRE-L
TRE-R
BASS-L2
BASS-L1
BASS-R1
BASS-R2
L-OUT
R-OUT
NC
NC
CLK
DATA
TONE CONTROL
BASS/TREBLE
SURROUND
INPUT
GAIN CONTROL
IGOUT-R
IGOUT-L
VOLIN-R
VOLIN-L
MUTE
MUTE
INPUT
GAIN
CONTROL
L ch
TONE CONTROL
BASS/TREBLE
R ch
MCU
I/F
0 - +12dB/2dB step
0 - +12dB
/2dB step
/2dB step
VOLUME
VOLUME
0 - -89dB.
0 - -89dB.
REF
INPUT
SELECTOR
INPUT
SELECTOR
SELECTOR
MODE
1
7
8
9
10
11
12
3
4
4
+
–
+
–
–
VCC2
CH-1
CH-2
L-OUT
L-BS
POWER GND
L-NF
L-IN
VCC1
R-OUT
R-BS
RIPPLE
R-NF
R-IN
R-OUT
R-BS
RIPPLE
R-NF
R-IN
2
5
6
6
ZS-S2iP
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• IC Pin Description
• IC701 BU9532KS2 (RF AMP, SYSTEM SERVO PROCESSOR, DIGITAL SIGNAL PROCESSOR)
(MAIN BOARD (2/4))
• IC701 BU9532KS2 (RF AMP, SYSTEM SERVO PROCESSOR, DIGITAL SIGNAL PROCESSOR)
(MAIN BOARD (2/4))
Pin No.
Pin Name
I/O
Description
1
AVDD1
I
Power supply pin (+3.3 V)
2
AC (I)
I
A+C RF signal input
3
BD (I)
I
B+D RF signal input
4
VBIAS (O)
O
VC voltage output
5
E (I)
I
E RF signal input
6
F (I)
I
F RF signal input
7
PKC (O)
O
RF signal peak detector capacitor fi tted
8
FEN (I)
I
Focus error amp input
9
FEO (O)
O
Focus error output
10
BTC (O)
O
RF signal bottom detector capacitor fi tted
11
PD (I)
I
Photo detector signal input
12
LD (O)
O
Laser diode drive signal outout
13
ASY (I)
I
Asymmentric correction input
14
PCO (O)
O
PLL PCO output
15
FCO (O)
O
PLL FCO-DAC output
16
AGND1
—
Ground pin
17
FDOUT (O)
O
Focus drive signal output
18
JUMPO (O)
O
track jump pulse drive signal input
19
TDOUT (O)
O
Tracking drive sigmal outout
20
SDIN (I)
I
Sled drive signal input
21
SDOUT (O)
O
Sled drive signal output
22
CLVOUT (O)
O
CLV drive signal output
23
CLK88 (O)
O
Not used in this set. (Open)
24
LON (O)
O
Not used in this set. (Open)
25
CLK (O)
O
Not used in this set. (Open)
26
SUBSYQ (O)
O
Sub code synchronous signal output
27
MCK (I)
I
Command transfer clock input
28
DIN (I)
I
Status and SUB-Q data input
29
DOUT (O)
O
Command data output
30
R/W (I)
I
Command read/write signal input
31
RESETX (I)
I
Reset signal input
32
BUSY (O)
O
BUSY signal output
33
MONI 0
I
Test input (Not used in this set. (pull down))
34
MONI 1
I
Muting signal input
35
XPCLK
O
XPCLK signal output
36
DVDD
—
Power supply pin (+3.3 V)
37
XI (I)
I
Main clock input (16.93 MHz)
38
XO (O)
O
Main clock output (16.93 MHz)
39
DGND
—
Ground pin
40
AVDD2
—
Power supply pin (+3.3V)
41
LDACO (O)
O
Audio L-CH output
42
VCDAC
O
Audio DAC reference voltage output
43
RDACO (O)
O
Audio R-CH output
44
AGND2
—
Ground pin
45
RFRPRFM (O)
O
RFRP capacitor fi tted
46
TZCRFM (O)
O
TZC capacitor fi tted
47
SC (O)
O
Scratch depth ajstment output
48
TEO (O)
O
Tracking error outpot
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