DOWNLOAD Sony ZS-M7 Service Manual ↓ Size: 14.64 MB | Pages: 91 in PDF or view online for FREE

Model
ZS-M7
Pages
91
Size
14.64 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
zs-m7.pdf
Date

Sony ZS-M7 Service Manual ▷ View online

– 100 –
– 102 –
– 101 –
r
  IC Block Diagrams – BD Section –
IC121  CXD2652AR
IC152  BH6511FS
100 99 98 97 96 95
94 93
EFMO
DVSS
TEST3
TEST2
TEST1
FGIN
SPFD
SPRD
92
SFDR
91
SRDR
90
FS4
89
FRDR
88
FFDR
87
DVDD
86
TFDR
85
TRDR
84
LDDR
83
APCREF
82
DTRF
81
CKRF
80
XLRF
79
F0CNT
78
ADFG
77
APC
76
DCHG
75 AUX2
74 TE
73 SE
72 AVSS
71 ADRB
70 ADRT
69 AVDD
68 ADIO
61 CLTV
60 FILO
59 FILI
58 PCO
57 PDO
55 RFI
56 AVSS
54 BIAS
53 AVDD
52 ASYI
51 ASYO
67 VC
66 AUX1
65 FE
64 ABCD
63 BOTM
62 PEAK
50
MVCI
49
D3
48
D2
47
D0
46
D1
45
XWE
44
XRAS
43
A09
42
XCAS
41
XOE
40
DVSS
39
A11
38
A08
37
A07
36
A06
35
A05
34
A04
33
A10
32
A00
31
A01
30
A02
29
A03
28
DVDD
26
XBCK
27
FS256
25
LRCK
24
DADT
23
ADDT
22
DOUT
21
DIN
20
D VSS
19
TESTG
18
XTSL
17
OSCO
16
OSCI
15
TX
14
XINT
13
RECP
12
DQSY
11
SQSY
10
XRST
9
SENS
8
SRDT
7
XLAT
6
SCLK
5
SWDT
4
MNT3
3
MNT2
2
MNT1
1
MNT0
PWM
GENERATOR
AUTO
SEQUENCER
SERVO
DSP
CPU I/F
MONITOR
CONTROL
SPINDLE
SERVO
EACH
BLOCK
EACH
BLOCK
DIGITAL
AUDIO
I/F
SAMPLING
RATE
CONVERTER
CLOCK
GENERATOR
SUBCODE
PROCESSOR
EACH
BLOCK
A/D
CONVERTER
ANALOG
MUX
EFM/ACIRC
ENCODER/
DECODER
APC
PLL
SHOCK RESISTANT
MEMORY CONTROLLER
ATRAC
ENCODER/DECODER
DRAM
ADIP
DEMODULATOR/
DECODER
COMP
ADDRESS/DATA BUS A00 - A11, D0 - D3
INTERFACE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
VG
IN4R
IN4F
VM4
OUT4F
PGND4
OUT4R
VM34
OUT3R
PGND3
OUT3F
VM3
IN3F
IN3R
PSB
CAPA–
CAPA+
IN2R
IN2F
VM2
OUT2F
PGND2
OUT2R
VM12
OUT1R
PGND1
OUT1F
VM1
IN1F
IN1R
V
DD
CHARGE
PUMP.
OSC
INTERFACE
AMP
INTERFACE
AMP
AMP
INTERFACE
PRE DRIVE
PRE DRIVE
PRE DRIVE
PRE DRIVE
AMP
INTERFACE
AMP
AMP
AMP
V
DD
PSB
AMP
IC101  CXA2523R
–1
–2
+
IVR
BB
+
IVR
AA
+
IVR
CC
+
IVR
DD
+
IVR
+
EE
EE'
EFB
TESW
PTGR
48
MORFO
47
MORFI
46
RFO
45
OPN
44
OPO
43
ADDC
42
COMPP
41
COMPO
40
AGCI
39
RF AGC
38
RF
37
PEAK
36 BOTM
35 ABCD
34 FE
33 AUX
32 ADFG
31 ADAGC
30 ADIN
29 ADFM
28 SE
27 CSLED
26 TE
25 WBLADJ
24
VCC
23
3TADJ
22
EQADJ
21
VREF
20
F0CNT
19
XSTBY
18
XLAT
17
SCLK
16
SWDT
15
TEMPR
14
TEMPI
13
GND
12
APCREF
11
APC
10
PD
9
F
8
E
7
D
6
C
5
B
4
A
3
VC
VI CONV
BGR
VREF
SCRI - PARA
DECODE
+
+
AUXSW
COMMAND
+
IVR
GSW IV
+
FF
FBAL
FF'
TG
SEA
+
+
–1
–2
TG
TEA
WBL
3T
EQ
+
+
+
+
+
+
+
+
DET
ADIP
AGC
WBL
BPF22
BPFC
ABCDA
FEA
WBL
ATA
+
CVB
+
RFA1
1
2


1
2
GRVA
CFST
RFA2
GRV
HLPT
PTGR
–2
–1
–1
–2
BOTTOM
PEAK
RF AGC
EQ
EQ
DET
P-P
WBL
3T
WBL
TEMP
PBH
+
USROP
+
USRC
3T
BPF3T
PEAK3T
1
I
2
J
r
  IC Block Diagrams – Tuner Section –
IC1  TA2008AN
IC2  BU2615FS
21
22
23
24
2
3
5
4
6
7
8
9
10
1
11
12
13
14
15
16
17
18
19
20
AM
RF
FM
RF
BUFF
BUFF
IF
BUFF
AF
BUFF
FM MPX
FM
MIX
FM
IF
AM
IF
AM
MIX
AM
DET
1/8DIV
MUTE
AGC
FM RF IN
GND1
MIX OUT
AGC
VCC2
FM IF IN
AM IF IN
GND2
QUAD
ST IND
L OUT
R OUT
AM RF IN
FM RF OUT
AM OSC
FM OSC
VCC1
OSC OUT
IF OUT
DET OUT
MPX IN
LPF1/BAND
LPF2/MO-ST
VCO
FM
DET
ST
DET
LEVEL
DET
AM
OSC
FM
OSC
AM/FM
ST/MONO
SW
11
17
18
19
20
3
5
4
6
7
8
9
10
12
13
14
15
2
16
1
X IN
X OUT
FM IN
AM IN
CE
CK
DA
CD
P 0
P 1
BAND
P 2
NU
P 3
LW-L
P 4
MW-L
P 6
FM-L
IF IN
VSS
VDD 2
VDD 1
PD 1
PD 2/ P 5
LOC/DX
20 BIT COUNT
I / O
CTL
 IF COUNT
CTL
SHIFT REGISTER LATCH
REFERENCE DIVIDER
PHASE
DET
PRESCALER
MAIN COUNT
BUFFER
ULLOCK
P5
r
 IC Block Diagrams (DG Section)
IC504  RH5RL33AA-T1
1
2
GND
VIN
OUT
3
VREF
– 103 –
r
  IC Block Diagrams – Main Section –
IC701  CXA1992BR
Charge
up
FEO
FEI
FDFCT
FGD
FLB
FE_O
FE_M
SRCH
TGU
TG2
FSET
TA_M
TA_O
SL_P
SL_M
SL_O
ISET
VCC
VCC
LOCK
CLK
XLT
DATA
XRST
C. OUT
SENS1
SENS2
FOK
CC2
CC1
CB
CP
RF_I
RF_O
RF_M
RFTC
LD
PDO
PD1
PD2
FE_
BIAS
F
E
EI
VEE
TEO
LPF1
TEI
ATSC
TZC
VC
FZC
TM2
VEE
VEE
TM3
TM5
TM4
TM6
VCC
VCC
TM7
ISET
TTL
IIL
IIL
TTL
IIL
TTL
IIL DATA REGISTER,
INPUT SHIFT REGISTER,
ADDRESS DECODER,
SENS SELECTOR,
OUTPUT DECODER
DFCTO IFB1-6
BAL1-4
TOG1-4
FS1-4
TG1-2
TM1-7 PS1-4
FOH
FOL
TGH
TGL
BALH
BALL
ATSC
TZC
FZC
FSET
TG2
VEE
VCC
FS1
FS2
FOCUS
PHASE COMPENSATION
DFCT
FS4
TRACKING 
PHASE COMPENSATION
TG1
TM1
DFCT
FZC COMP.
VEE
VCC
VCC
TDFCT
TZC COMP.
ATSC
WINDOW
COMP.
E-F BALANCE
WINDOW COMP.
TRK. GAIN
WINDOW COMP.
FO. BIAS
WINDOW 
COMP.
VEE
TGFL
TOG1
TOG2
TOG3
TOG4
BAL1
BAL2
BAL3
BAL4
IFB1
IFB2
IFB3
IFB4
IFB5
IFB6
FE AMP
VEE
E IV AMP
F IV AMP
VCC
APC
VCC
VEE
LASER POWER CONTROL
VEE
PD1 IV
AMP
PD2 IV
AMP
RF 
SUMMING 
AMP
VCC
VEE
VEE
LEVEL S VEE
MIRR
VCC
DFCT
FOK
VCC
LDON
LPCL
LPC
TGFL
MIRR
DFCT1
CC1
1
2
3
4
5
6
7
8
9
10
11
12
13
26
39
40
41
42
43
44
45
46
47
48
49
50
51
52
38
37
36
35
34
33
32
31
30
29
28
27
24
24
23
22
21
20
19
18
17
16
15
14
– 104 –
IC703  CXD2589Q
CLOCK
GENERATOR
OSC
PWM
ASYMMETRY
CORRECTOR
DIGITAL
PLL
SERVO
AUTO
SEQUENCER
EFM
DEMODULATOR
SUB CODE
PROCESSOR
TIMING
LOGIC
CPU
INTERLACE
ERROR
CORRECTOR
16K
RAM
D/A
INTERFACE
DIGITAL
OUT
DIGITAL
CLV
SERIAL-IN
INTERFACE
OVER SAMPLING
DIGITAL FILTER
3rd-ORDER
NOISE SHAPER
PWM
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
59 58 57
56
55
54 53 52 51 50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
23
22
21
VSS
LMUTE
RMUTE
SQCK
SQSO
SENS
DATA
XLAT
CLOK
SEIN
CNIN
DATO
XLTO
CLKO
SPOA
SPOB
XLON
FOK
VDD
VSS
MDP
PWMI
TES0
TES1
VPCO1
VCKI
VCTL
V16M
PCO
FILO
FILI
AVSS
CLTV
AVDD
RF
BIAS
ASYI
ASYO
LRCK
LRCKI
PCMD
PCMD
I
BCK
BCKI
VSS
VDD
XUGF
XPCK
GFS
C2PO
XTSL
C4M
DOUT
EMPH
ENPHI
WFCK
SCOR
SBSO
EXCK
VSS
VDD
SYSM
AVSS
AVDD
AOUT1
AIN1
LOUT1
AVSS
XVDD
XTAI
XTAO
XVSS
AVSS
LOUT2
AIN2
AOUT2
AVDD
AVSS
XRST
VDD
– 105 –
IC702  BA6898FP
IC301  TDA7439D013TR
LEVEL SHIFT
VCC
DRIVER MUTE
VCC
LEVEL SHIFT
LEVEL SHIFT
LEVEL SHIFT
THERMAL
SHUT DOWN
REG VOLTAGE DOWN,
BIAS VOLTAGE DOWN,
THERMAL SHUT DOWN
MONITOR
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
SL –
SL +
SL IN
RESET
REGB
REGO
MUTE
GND
(SP IN)
SP IN
SP –
SP +
GND
SPO
GND
F –
F +
FIN
(FIN)
VRE
F
VCC
VCC
(TIN)
TIN
T –
T +
VRE
F
SP I
DRIVE
DRIVE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
17
15
11
12
13
14
10
8
9
VOLUME
INPUT
MULTIPLEXER
GAIN
VREF
SUPPLY
R IN4
LOUT
ROUT
AGND
VS
CREF
SDA
SCL
DIG-GND
TREBLE (R)
TREBLE (L)
MIN (L)
MOUT (L)
BOUT (L)
BIN (L)
R IN3
R IN2
R IN1
L IN1
L IN2
L IN3
L IN4
MUXOUTL
MUXOUTR
MIN (R)
MOUT (R)
BIN (R)
BOUT (R)
SPKA ATT
RIGHT
TCBUS
DECODER •
LATCH
SPKA ATT
LEFT
0/30dB
2dB STEP
TREBLE
MIDDLE
BASS
VOLUME
TREBLE
MIDDLE
BASS
18
19
20
21
22
23
24
25
26
27
28
6
7
5
4
G
2
3
1
G
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