Sony ZS-M7 Service Manual ▷ View online
– 41 –
Pin No.
Pin name
I/O
Description
51
ASYO
O
Playback EFM duplex signal output.
52
ASYI
I(A)
Playback EFM comparator slice level input.
53
AVDD
–
Power supply for analog (+3V).
54
BIAS
I(A)
Playback EFM comparator bias current input.
55
RFI
I(A)
Playback EFM RF signal input.
56
AVSS
–
Ground for analog.
57
PDO
O(3)
Phase comparison output for clock playback analog PLL of playback EFM (not used).
58
PCO
O(3)
Phase comparison output for record/playback EFM system master PLL.
59
FILI
I(A)
Filter input for record/playback EFM system master PLL.
60
FILO
O(A)
Filter output for record/playback EFM system master PLL.
61
CLTV
I(A)
Internal VCO control voltage input for record/playback EFM system master PLL15.
62
PEAK
I(A)
Light volume signal peak hold input from CXA2523AR.
63
BOTM
I(A)
Light volume signal bottom hold input from CXA2523AR.
64
ABCD
I(A)
Light volume signal input from CXA2523AR.
65
FE
I(A)
Focus error signal input from CXA2523AR.
66
AUX1
I(A)
Auxiliary A/D input.
67
VC
I(A)
Midpoint voltage (+1.5V) input from CXA2523AR.
68
ADIO
O(A)
A/D converter input signal monitor output (not used).
69
AVDD
–
Power supply for analog (+3V).
70
ADRT
I(A)
A/D converter operating range upper limit voltage input (Fixed at “H”) .
71
ADRB
I(A)
A/D converter operating range lower limit voltage input (Fixed at “L”).
72
AVSS
–
Ground for analog.
73
SE
I(A)
Thread error signal input from CXA2523AR.
74
TE
I(A)
Tracking error signal input from CXA2523AR.
75
AUX2
I(A)
Auxiliary A/D input (Fixed at “L”).
76
DCHG
I(A)
Connected to +3V power supply.
77
APC
I(A)
Laser digital APC error signal input (Fixed at “L”).
78
ADFG
I(S)
ADIP duplex FM signal input (22.05±1kHz) from CXA2523AR.
79
F0CNT
O
Filter f0 control output from CXA2523AR.
80
XLRF
O
Control latch output from CXA2523AR.
81
CKRF
O
Control clock output from CXA2523AR.
82
DTRF
O
Control data output from CXA2523AR.
83
APCREF
O
Laser APC reference PWM output.
84
LDDR
O
Laser digital APC PWM output (not used).
85
TRDR
O
Tracking servo drive PWM output (-).
86
TFDR
O
Tracking servo drive PWM output (+).
87
DVDD
–
Power supply for digital (+3V).
88
FFDR
O
Focus servo drive PWM output (+).
89
FRDR
O
Focus servo drive PWM output (-).
90
FS4
O
176.4kHz clock signal output (X’tal) (not used).
91
SRDR
O
Thread servo drive PWM output (-).
92
SFDR
O
Thread servo drive PWM output (+).
93
SPRD
O
Spindle servo drive PWM output (-).
94
SPFD
O
Spindle servo drive PWM output (+).
95
FGIN
I(S)
Spindle CAV servo FG input.
96–98
TEST1–TEST3
I
Test input pins (Fixed at “L”).
99
DVSS
–
Ground for digital.
100
EFMO
O
EFM output during recording.
EFM : Eight to Fourteen Modulation
PLL : Phase Locked Loop
VCO : Voltage Controlled Oscillator
PLL : Phase Locked Loop
VCO : Voltage Controlled Oscillator
– 42 –
Pin No.
Pin name
I/O
Description
1
DAOUT0
–
not used (OPEN).
2
DAOUOT1
–
not used (OPEN).
3
KEY0
–
Reserved (“H” level).
4
KEY1
–
Reserved (“H” level).
5
KEY2
–
Reserved (“H” level).
6
CHACK IN
I
Detection input from chucking-in switch (S685).
7
PACK IN
I
Detection input from back-in switch (not used).
8
PACK OUT
I
Detection input from back-out switch (S686).
9
–
not used (ground connection).
10
–
not used (ground connection).
11
AVSS
–
ground for analog.
12
X INT
I
Interrupt status input from digital signal processor IC (IC121).
13
PDOWN
I
Power cutoff signal input from master control IC (IC801).
14
–
Reserved (ground connection).
15
SQSY
I
Subcode Q-SYNC (SCOR) input from digital signal processor IC (IC121).
16
DQSY
I
Digital-in U-bit format subcode input from digital signal processor IC (IC121).
17
–
Reserved (ground connection).
18
–
Reserved (ground connection).
19
–
Reserved (ground connection).
________
20
SYS-RST
I
System reset input pin “L”: Reset.
21
TEST
I
Test mode pin “L”: Normal mode, “H”: Test mode.
22
+3.3V
–
Power supply terminal (VCC).
23
VBAT
I
Power supply pin for internal RTC and RAM.
24
XOUT-T
O
Sub-clock connector pin (32.768kHz).
25
XINT-T
I
Sub-clock connector pin (32.768kHz).
26
GND
–
Power supply terminal (ground).
27
XOUT
O
Main clock connector pin (12MHz).
28
XIN
I
Main clock connector pin (12MHz).
29
EXEM
I
Switch pin for External ROM mode and Internal ROM mode.
30
S1
–
not used (OPEN).
31
–
Reserved (ground connection).
32
SENS
I
Internal status (SENSE) input from digital signal processor IC (IC121).
33
SHOCK
I
Track-jump detection signal input from digital signal processor IC (IC121).
34
–
Reserved (ground connection).
35
–
Reserved (ground connection).
36
STB
O
Power ON/OFF control signal output.
37
REC P
I
Detection input from REC switch (S688).
38
PB P
I
Detection input from PB switch (S687).
39
LD LOW
O
Loading motor control signal output.
40
NC
–
not used (OPEN).
41
MNT2
I
Monitor 2 input from digital signal processor IC (IC121).
42
MNT3
I
Monitor 3 input from digital signal processor IC (IC121).
43
LEDO
–
not used (OPEN).
44
–
Reserved (ground connection).
45
–
Reserved (ground connection).
46
RST LOW
–
not used (OPEN).
47
GND
–
Power supply terminal (ground).
48
+3.3V
–
Power supply terminal (VCC).
49
SNG/CHG
–
Reserved (ground connection).
50
JOG1
–
Reserved (ground connection).
DG BOARD (2/2) IC502 SYSYTEM CONTROL (RU8X12MF-0021)
– 43 –
– 45 –
– 44 –
Pin No.
Pin name
I/O
Description
51
JOG0
–
Reserved (ground connection).
52
SDA
I/O
Serial data I/O with EEPROM (IC171).
53
SCL
O
Serial clock output to EEPROM (IC171).
54
2M/4M
–
Reserved (“H” level).
55
–
Reserved (ground connection).
56
–
Reserved (ground connection).
57
RXD (UART)
O
Communication with master control IC (IC801) and UART receive output.
58
TXD (UART)
I
Communication with master control IC (IC801) and UART send input.
59
RTS (T)
I
UART send request input from master control IC (IC801).
60
CTS (R)
O
UART send request output to master control IC (IC801).
61
AUBIT0
–
Reserved (“H” level).
62
AUBIT1
–
Reserved (ground connection).
63
CLKSET0
–
Reserved (ground connection).
64
CLKSET1
–
Reserved (ground connection).
65
GND
–
Power supply pin (ground).
66
+3.3V
–
power supply pin (VCC).
67
SCLK
O
Serial clock output to digital signal processor IC (IC201).
68
SWDT
O
Write data signal output to digital signal processor IC (IC121).
69
SRDT
I
Read data signal input from digital signal processor IC (IC121).
70
EMP
O
Delmphasis ON/OFF control signal output.
71
SCK1
–
not used (OPEN).
72
SOUT1
–
not used (OPEN).
73
SIN1
–
not used (OPEN).
74
CSB
–
Reserved (VCC connection).
75
LDON
O
Laser ON/OFF control signal output.
76
PIT/GRV
–
not used (OPEN).
77
FOK
I
Focus OK signal input from digital signal processor IC (IC121).
78
–
not used (OPEN).
79
LOCK
–
not used (OPEN).
80
WRPWR
O
Laser power switch signal output to digital signal processor IC (IC121).
________
81
DIG-RST
O
Reset signal output.
82
–
not used (OPEN).
_______
83
DA-RST
O
Reset signal output to D/A and A/D converters “L”: reset.
84
DSEL-A
–
not used (OPEN).
85
DSEL-B
–
not used (OPEN).
86
MOD
O
MD module ON/OFF control signal output.
__
87
REC/PB
–
not used (OPEN).
88
–
not used (OPEN).
89
SCTX
O
Record data output authorization signal output.
90
XLATCH
O
Serial latch signal output to digital signal processor IC (IC121).
91
–
not used (OPEN).
92
–
not used (OPEN).
93
AMUTE
–
not used (OPEN).
94
LD OUT
O
Loading motor F control signal output.
95
LD IN
O
Loading motor F control signal output.
96
LIMIT IN
I
Detection input from limit switch (S681).
97
PROTECT
I
Record tab detection input from disk write-protect switch (S683).
98
REFLECT
I
Disk reflection rate detection input from reflect switch (S682).
99
GND
–
Power supply terminal (ground).
100
+3.3V
–
Power supply terminal (VCC).
Pin No.
Pin name
I/O
Description
1
PACON
O
Power amplifier control output.
2
MEGABASE
O
Mega-bus control output.
3
RECH
O
A/D converter select output.
4
STXD
O
Communication with MD and UART send output.
5
SRXD
I
Communication with MD and UART receive input.
6
SCTS
I
UART send request input from MD.
7
SRTS
O
UART send request output to MD.
8
MDH
O
D/A converter select output.
9
PDOWN
O
Notification of power cutoff to MD.
10
MDRST
O
Reset MD microcomputer.
11
PCON
O
Power supply control output.
12
OPEN
O
CD tray control output H: Open.
13
CLOSE
O
CD tray control output H: Close.
14
XRST
O
CD system reset output.
15
MDATA
O
CD serial data output.
16
SENSE1
I
CD sense input 1.
17
MCLK
O
CD serial clock output.
18
XLT
O
CD system latch output.
19
–
not used.
20
SENCE2
I
CD sense input 1.
21
TEST
I
Test mode input. “L”: Reset
22
RSMK1
I
Radio-directed setting 1 (+5V connection).
23
RSMK2
I
Radio-directed setting 2 (ground connection).
24
RSMK3
I
Radio-directed setting 3 (ground connection).
25
ACCHK
I
AC power supply detection input. L: AC H: No AC
26
LEDMD
O
LED on during MD.
27
LEDCD
O
LED on during CD.
28
LEDRADIO
O
LED on during radio.
29
SHIFT
O
Shift system clock.
30
RST
I
Hardware reset pin. “L”: Reset
31
EXTAL
I
System clock (5MHz) oscillation input.
32
XTAL
O
System clock (5MHz) oscillation output.
33
VSS
Ground.
34
TX
O
Time clock (32.768kHz) oscillation output.
35
TEX
I
Time clock (32.768kHz) oscillation input.
36
AVSS
Ground for A/D converter.
37
AVREF
I
A/D converter reference voltage input.
38
KEY1
I
Key input (12 stage input) 1.
39
KEY2
I
Key input (12 stage input) 2.
40
KEY3
I
Key input (12 stage input) 3.
41
–
not used (OPEN).
42
–
not used (OPEN).
43
–
not used (OPEN).
44
REGCHK
I
Regulator voltage check input.
45
OPN/CLS
I
CD tray status detection input.
46
FLRST
O
FL microcomputer reset.
47
FLCS2
O
FL name communication and chip select output.
48
FLSCK2
O
FL name communication and clock output.
49
FLDI2
I
FL name communication and data input.
50
FLDO2
O
FL name communication and data output.
MAIN BOARD (2/2) IC801 SYSYTEM CONTROL (CXP84648-037Q)
Pin No.
Pin name
I/O
Description
51
FLSCK1
O
Communication with FL microcomputer and clock output.
52
FLCS1
O
FL microcomputer chip select output.
53
FLDT1
O
Communication with FL microcomputer and data output.
54
JOG1
I
JOG dial rotation detection 1 input.
55
JOG2
I
JOG dial rotation detection 2 input.
56
RMC
I
remote control signal input.
57
RDI
I
Radio PLL data input.
58
RDO
O
Radio PLL data output.
59
RSCK
O
Radio PLL clock output.
60
RCE
O
Radio PLL chip enable output.
61
SCOR
I
CD score input.
62
FOK
I
CDFOK input.
63
–
not used (OPEN).
64
EPSD
I/O
EEPROM data I/O.
65
SQCK
O
CDSUBQ clock output.
66
SUBQ
I
CDSUBQ data input.
67
EPSK
O
EEPROM clock output.
68
ST
I
Radio stereo detection. “L”: Mono
69
9/10
I
Radio AM station interval switch. “L”: Set to 9kHz
70
RMUTE
O
Radio mute output.
71
EPCS
O
EEPROM chip select output.
72
VDD
–
Power supply terminal (+5V).
73
NC
–
VDD connection.
74
MD
–
not used (OPEN).
75
CD
O
CD function output.
76
RADIO
O
Radio function output.
77
XLINE
O
Line function output.
78
VOCLK
O
Serial data output for volume.
79
AMUTE
O
Audio mute output.
80
VOLDATA
O
Serial clock output for volume.
– 46 –
– 48 –
– 47 –
6-2. BLOCK DIAGRAM (1)
ZS-M7
• Signal path.
F
: FM
E
: MD PLAY
q
: MD REC
J
: CD
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