Sony STR-KIV300 Service Manual ▷ View online
STR-KIV300
57
Pin No.
Pin Name
I/O
Description
AB11
DDRVCCIO1
-
Power supply terminal (+1.5V)
AB12
DGND12_K
-
Ground terminal
AB13
DDRVCCIO1
-
Power supply terminal (+1.5V)
AB14,
AB15
DGND12_K
-
Ground terminal
AB17
DDRVCCIO1
-
Power supply terminal (+1.5V)
AB18,
AB19
DGND12_K
-
Ground terminal
AB20
AVSS33_LDO
-
Ground terminal
AB21
AVDD12_LDO
-
Not used
AB23
MDIO
-
Not used
AB24
CEC
-
Not used
AB25
HDMISCK
I/O
Two-way I2C clock bus with the HDMI ARC OUT connector
AB26
HDMISD
I/O
Two-way I2C data bus with the HDMI ARC OUT connector
AB27
TXVN_0
-
Not used
AB28
TXVP_0
-
Not used
AC1
NC
-
Not used
AC2
NC
-
Not used
AC3
DDRVCCIO1
-
Power supply terminal (+1.5V)
AC4
DGND12_K
-
Ground terminal
AC5
AVDD33_MEMPLL
-
Power supply terminal (+3.3V)
AC7
DDRVREF_C
I
Reference voltage (+0.75V) input terminal for SD-RAM
AC8
RDQM2
O
Data mask signal output to the SD-RAM
AC9
DGND12_K
-
Ground terminal
AC10
RBA0
O
Bank address signal output to the SD-RAM
AC11
DDRVCCIO1
-
Power supply terminal (+1.5V)
AC12
RA6
O
Address signal output to the SD-RAM
AC14
DDRVCCIO1
-
Power supply terminal (+1.5V)
AC15
RBA1
O
Bank address signal output to the SD-RAM
AC17,
AC18
RDQ10, RDQ15
I/O
Two-way data bus with the SD-RAM
AC19
DDRVCCIO1
-
Power supply terminal (+1.5V)
AC21
NFRBN2
-
Not used
AC24
GPIO27
O
WOL (wake-on-LAN) wake-up signal output to the system controller "H": wake-up
AC25
DDC_SCL_RX2
O
I2C clock signal output to the HDMI IN 2 connector
AC26
CEC2
-
Not used
AC27
TXVN_1
-
Not used
AC28
TXVP_1
-
Not used
AD1
NC
-
Not used
AD2, AD3
NC
-
Not used
AD4
AVSS33_MEMPLL
-
Ground terminal
AD8
RA13
O
Address signal output to the SD-RAM
AD9
RRESET
O
Reset signal output to the SD-RAM "L": reset
AD10
RCAS_
O
Column address signal output to the SD-RAM
AD11 to
AD15
RA14, RA8, RA1, RA10,
RA12
O
Address signal output to the SD-RAM
AD16 to
AD18
RDQ8, RDQ12, RDQ14 I/O
Two-way data bus with the SD-RAM
AD19
DDRVCCIO1
-
Power supply terminal (+1.5V)
AD20
AVDD33_LDO
-
Power supply terminal (+3.3V)
AD21
NFRBN
O
Ready/busy selection signal output to the NAND fl ash "L": busy, "H": ready
AD22
NFCLE
O
Command latch enable signal output to the NAND fl ash
AD23
MDC
-
Not used
AD24
DDC_SDA_RX2
I/O
Two-way I2C data bus with the HDMI IN 2 connector
AD25
PWR5V_RX
I
Power supply voltage (+5V) input from the HDMI IN 1 connector
STR-KIV300
58
Pin No.
Pin Name
I/O
Description
AD26
HTPLG_RX_2
O
Hot plug detection signal output to the HDMI IN 2 connector
AD27
REXT
-
External reference resistor connection terminal
AD28
HTPLG
I
Hot plug detection signal input from the HDMI ARC OUT connector
AE3
NC
-
Not used
AE5
DDRVCCIO1
-
Power supply terminal (+1.5V)
AE6 to AE8
RDQ29, RDQ31,
RDQ30
I/O
Two-way data bus with the SD-RAM
AE9
RWE_
O
Write enable signal output to the SD-RAM
AE10
RODT
O
On die termination enable signal output to the SD-RAM
AE11
RRAS_
O
Row address signal output to the SD-RAM
AE12
RA3
O
Address signal output to the SD-RAM
AE13
RCSX_
-
Not used
AE14
RA4
O
Address signal output to the SD-RAM
AE16
RDQ11
I/O
Two-way data bus with the SD-RAM
AE17
RDQM1
O
Data mask signal output to the SD-RAM
AE18
RDQ13
I/O
Two-way data bus with the SD-RAM
AE19,
AE20
DVCC33_IO_STB
-
Power supply terminal (+3.3V)
AE21
NFREN
O
Read enable signal output to the NAND fl ash
AE22
NFCEN2
-
Not used
AE23
NFD0
I/O
Two-way data bus with the NAND fl ash
AE24
NFWEN
O
Write enable signal output to the NAND fl ash
AE25
HTPLG_RX
O
Hot plug detection signal output to the HDMI IN 1 connector
AE26
PWR5V_RX2
I
Power supply voltage (+5V) input from the HDMI IN 2 connector
AF1, AF2
TP_MEMPLL,
TN_MEMPLL
-
Not used
AF3
NC
-
Not used
AF4
RDQ25
I/O
Two-way data bus with the SD-RAM
AF5
DGND12_K
-
Ground terminal
AF6
RDQ28
I/O
Two-way data bus with the SD-RAM
AF7
DDRVCCIO1
-
Power supply terminal (+1.5V)
AF8, AF9
RDQ20, RDQ22
I/O
Two-way data bus with the SD-RAM
AF10
DDRVCCIO1
-
Power supply terminal (+1.5V)
AF11, AF12
RA9, RA5
O
Address signal output to the SD-RAM
AF13
RCS_
O
Chip select signal output to the SD-RAM
AF14 to
AF16
RDQ3, RDQ1, RDQ9
I/O
Two-way data bus with the SD-RAM
AF17, AF18
DDRVCCIO1
-
Power supply terminal (+1.5V)
AF20
RDQ5
I/O
Two-way data bus with the SD-RAM
AF21
NFD6
I/O
Two-way data bus with the NAND fl ash
AF22
NFCEN
O
Chip enable signal output to the NAND fl ash
AF23
NFD1
I/O
Two-way data bus with the NAND fl ash
AF24
NFALE
O
Address latch enable signal output to the NAND fl ash
AF25
UARXD
-
Not used
AF26
RESET_
I
Reset signal input from the system controller "L": reset
AF27
DDC_SDA_RX
I/O
Two-way I2C data bus with the HDMI IN 1 connector
AF28
DDC_SCL_RX
O
I2C clock signal output to the HDMI IN 1 connector
AG1 to AG4
RDQ17, RDQ16,
RDQ26, RDQ27
I/O
Two-way data bus with the SD-RAM
AG5
RDQS2
O
Data strobe signal (positive) output to the SD-RAM
AG6
RCLK1
O
Clock signal (positive) output to the SD-RAM
AG7
RDQS3_
O
Data strobe signal (negative) output to the SD-RAM
AG8
RDQ21
I/O
Two-way data bus with the SD-RAM
AG10
RBA2
O
Bank address signal output to the SD-RAM
STR-KIV300
59
Pin No.
Pin Name
I/O
Description
AG11,
AG13
RA2, RA11
O
Address signal output to the SD-RAM
AG14
RDQ0
I/O
Two-way data bus with the SD-RAM
AG16
RDQS0
O
Data strobe signal (positive) output to the SD-RAM
AG17
RCLK0
O
Clock signal (positive) output to the SD-RAM
AG18
RDQS1_
O
Data strobe signal (negative) output to the SD-RAM
AG19,
AG20
RDQ7, RDQ4
I/O
Two-way data bus with the SD-RAM
AG21 to
AG23
NFD7, NFD4, NFD2
I/O
Two-way data bus with the NAND fl ash
AG25
GPIO8
O
VBUS on/off control signal output terminal for WLAN/BT COMBO card "H": VBUS on
AG26
VCLK
O
Serial data transfer clock signal output to the system controller
AG27
VDATA
I
Serial data input from the system controller
AG28
LCDRD
O
Serial data output to the system controller
AH1 to AH3
RDQ18, RDQ19,
RDQ24
I/O
Two-way data bus with the SD-RAM
AH4
RDQM3
O
Data mask signal output to the SD-RAM
AH5
RDQS2_
O
Data strobe signal (negative) output to the SD-RAM
AH6
RCLK1_
O
Clock signal (negative) output to the SD-RAM
AH7
RDQS3
O
Data strobe signal (positive) output to the SD-RAM
AH8
RDQ23
I/O
Two-way data bus with the SD-RAM
AH10,
AH11
RA0, RA7
O
Address signal output to the SD-RAM
AH13
RCKE
O
Clock enable signal output to the SD-RAM
AH14
RDQ2
I/O
Two-way data bus with the SD-RAM
AH16
RDQS0_
O
Data strobe signal (negative) output to the SD-RAM
AH17
RCLK0_
O
Clock signal (negative) output to the SD-RAM
AH18
RDQS1
O
Data strobe signal (positive) output to the SD-RAM
AH19
RDQM0
O
Data mask signal output to the SD-RAM
AH20
RDQ6
I/O
Two-way data bus with the SD-RAM
AH22,
AH23
NFD5, NFD3
I/O
Two-way data bus with the NAND fl ash
AH25
OPWRSB
O
Power control signal output to the system controller
AH26
UATXD
-
Not used
AH27
VSTB
-
Not used
AH28
IR
-
Not used
STR-KIV300
60
MB1306 BOARD (1/7) IC102, IC103 H5TQ2G63FFR-PBCR (DDR3 SDRAM)
Pin No.
Pin Name
I/O
Description
A1
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
A2
DQU5
I/O
Data Input/output: Bi-directional data bus.
A3
DQU7
I/O
Data Input/output: Bi-directional data bus.
A4
NO_USE
-
Not used
A5
NO_USE
-
Not used
A6
NO_USE
-
Not used
A7
DQU4
I/O
Data Input/output: Bi-directional data bus.
A8
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
A9
VSS
-
Ground
B1
VSSQ
-
DQ Ground
B2
VDD
-
Power Supply: 1.5V +/-0.075
B3
VSS
-
Ground
B4
NO_USE
-
Not used
B5
NO_USE
-
Not used
B6
NO_USE
-
Not used
B7
DQSU
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
B8
DQU6
I/O
Data Input/output: Bi-directional data bus.
B9
VSSQ
-
DQ Ground
C1
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
C2
DQU3
I/O
Data Input/output: Bi-directional data bus.
C3
DQU1
I/O
Data Input/output: Bi-directional data bus.
C4
NO_USE
-
Not used
C5
NO_USE
-
Not used
C6
NO_USE
-
Not used
C7
DQSU
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
C8
DQU2
I/O
Data Input/output: Bi-directional data bus.
C9
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
D1
VSSQ
-
DQ Ground
D2
VDDQ
-
DQ Power Supply: 1.5V +/-0.075V
D3
DMU
I
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both adges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by Mode
Register A11 setting in MR1.
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both adges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by Mode
Register A11 setting in MR1.
D4
NO_USE
-
Not used
D5
NO_USE
-
Not used
D6
NO_USE
-
Not used
D7
DQU0
I/O
Data Input/output: Bi-directional data bus.
D8
VSSQ
-
DQ Ground
D9
VDD
-
Power Supply: 1.5V +/-0.075
E1
VSS
-
Ground
E2
VSSQ
-
DQ Ground
E3
DQL0
I/O
Data Input/output: Bi-directional data bus.
E4
NO_USE
-
Not used
E5
NO_USE
-
Not used
E6
NO_USE
-
Not used
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