Sony STR-DN850 Service Manual ▷ View online
STR-DN850
73
Pin No.
Pin Name
I/O
Description
C16
RX_HPD
O
Hot plug detection signal output to the HDMI transceiver
C17
AVDD1
-
Power supply terminal (+3.3V)
C18, C19
GND
-
Ground terminal
C20, C21
AVDD1
-
Power supply terminal (+3.3V)
C22, C23
DAC5, DAC6
O
Component video signal output to the video input selector
D1
OSD_IN[16]/
EXT_DIN[0]
I
OSD video data or video data input terminal Not used
D2
OSD_IN[17]/
EXT_DIN[1]
I
OSD video data or video data input terminal Not used
D3
OSD_IN[18]/
EXT_DIN[2]
I
OSD video data or video data input terminal Not used
D4
GND
-
Ground terminal
D5
DVDD_IO
-
Power supply terminal (+3.3V)
D6
MCLK
I
Master clock signal input from the HDMI transceiver
D7
SDA
I/O
Two-way I2C serial data with the video system controller, HDMI transceiver and HDMI input
selector
selector
D8
/CS1
I
Chip select signal input from the video system controller
D9
GND
-
Ground terminal
D10
INT1
O
Interrupt signal output to the video system controller (for HDMI transmitter)
D11
INT2
O
Interrupt signal output to the video system controller (for HDMI receiver)
D12
DVDD_IO
-
Power supply terminal (+3.3V)
D13
TEST1
-
Test terminal
D14, D15
NC
-
Not used
D16
RX_5V
I
Power supply (+5V) input terminal
D17, D18
NC
-
Not used
D19
RTERM
-
External resistor connection terminal
D20, D21
AVDD2
-
Power supply terminal (+3.3V)
D22
DAC1
O
Composite video signal output to the video input selector
D23
DAC2
O
Analog video signal output terminal Not used
E1
OSD_IN[13]/
VBI_SCK
I
OSD video data or serial data transfer clock signal input terminal Not used
E2
OSD_IN[14]/
VBI_MOSI
I
OSD video data or serial data input terminal Not used
E3
OSD_IN[15]/
VBI_/CS
I
OSD video data or chip select signal input terminal Not used
E4
DVDD_IO
-
Power supply terminal (+3.3V)
E20
TEST2
-
Test terminal
E21
GND
-
Ground terminal
E22
COMP2
-
External capacitor connection terminal
E23
DAC3
O
Analog video signal output terminal Not used
F1 to F4
OSD_IN[9] to
OSD_IN[12]
I
OSD video signal input terminal Not used
F20
RSET2
-
External resistor connection terminal
F21
PVDD3
-
Power supply terminal (+1.8V)
F22
GND
-
Ground terminal
F23
CEC1
O
HDMI CEC data output terminal Not used
G1 to G4
OSD_IN[5] to
OSD_IN[8]
I
OSD video signal input terminal Not used
G7 to G9
GND
-
Ground terminal
G10
DVDD
-
Power supply terminal (+1.8V)
G11, G12
GND
-
Ground terminal
G13
DVDD
-
Power supply terminal (+1.8V)
G14 to
G17
GND
-
Ground terminal
G20, G21
ELPF1, ELPF2
-
External loop fi lter connection terminal
G22
GND
-
Ground terminal
G23
AVDD3
-
Power supply terminal (+1.8V)
H1 to H4
OSD_IN[1] to
OSD_IN[4]
I
OSD video signal input terminal Not used
STR-DN850
74
Pin No.
Pin Name
I/O
Description
H7 to H17
GND
-
Ground terminal
H20, H21
GND
-
Ground terminal
H22
TX1_2+
O
TMDS data (positive) output to the HDMI OUT A ARC connector
H23
TX1_2–
O
TMDS data (negative) output to the HDMI OUT A ARC connector
J1
DE
I
Data enable signal input from the video A/D converter
J2
HS
I
Horizontal sync signal input from the video A/D converter
J3
OSD_HS
I
Horizontal sync signal input terminal Not used
J4
OSD_IN[0]
I
OSD video data input terminal Not used
J7
DVDD
-
Power supply terminal (+1.8V)
J8 to J16
GND
-
Ground terminal
J17
DVDD
-
Power supply terminal (+1.8V)
J20
DDC1_SDA
I/O
I2C serial data bus with the HDMI OUT A ARC connector
J21
GND
-
Ground terminal
J22
TX1_1+
O
TMDS data (positive) output to the HDMI OUT A ARC connector
J23
TX1_1–
O
TMDS data (negative) output to the HDMI OUT A ARC connector
K1
VS
I
Vertical sync signal input from the video A/D converter
K2
PCLK
I
Pixel clock signal input from the video A/D converter
K3, K4
DVDD_IO
-
Power supply terminal (+3.3V)
K7 to K17
GND
-
Ground terminal
K20
DDC1_SCL
O
I2C serial data transfer clock signal output to the HDMI OUT A ARC connector
K21
GND
-
Ground terminal
K22
TX1_0+
O
TMDS data (positive) output to the HDMI OUT A ARC connector
K23
TX1_0–
O
TMDS data (negative) output to the HDMI OUT A ARC connector
L1 to L4
P[32] to P[35]
I
Digital video signal input terminal Not used
L7
DVDD
-
Power supply terminal (+1.8V)
L8 to L17
GND
-
Ground terminal
L20
HPD_TX1
I
Hot plug detection signal input from the HDMI OUT A ARC connector
L21
GND
-
Ground terminal
L22
TX1_C+
O
TMDS clock (positive) signal output to the HDMI OUT A ARC connector
L23
TX1_C–
O
TMDS clock (negative) signal output to the HDMI OUT A ARC connector
M1 to M4
P[28] to P[31]
I
Digital video signal input terminal Not used
M7 to M17
GND
-
Ground terminal
M20
R_TX1
-
External resistor connection terminal
M21
PVDD4
-
Power supply terminal (+1.8V)
M22
HEAC_1+
I
HEAC (positive) signal input terminal Not used
M23
HEAC_1–
I
HEAC (negative) signal input terminal Not used
N1 to N4
P[24] to P[27]
I
Digital video signal input terminal Not used
N7 to N17
GND
-
Ground terminal
N20
CEC2
O
HDMI CEC data output terminal Not used
N21
PVDD5
-
Power supply terminal (+1.8V)
N22
AVDD3
-
Power supply terminal (+1.8V)
N23
NC
-
Not used
P1 to P4
P[20] to P[23]
I
Digital video signal input from the video A/D converter
P7
DVDD
-
Power supply terminal (+1.8V)
P8 to P16
GND
-
Ground terminal
P17
DVDD
-
Power supply terminal (+1.8V)
P20
DDC2_SCL
O
I2C serial data transfer clock signal output to the HDMI OUT B connector
P21
GND
-
Ground terminal
P22
TX2_2+
O
TMDS data (positive) output to the HDMI OUT B connector
P23
TX2_2–
O
TMDS data (negative) output to the HDMI OUT B connector
R1 to R4
P[16] to P[19]
I
Digital video signal input from the video A/D converter
R7 to R17
GND
-
Ground terminal
R20
DDC2_SDA
I/O
I2C serial data bus with the HDMI OUT B connector
R21
GND
-
Ground terminal
R22
TX2_1+
O
TMDS data (positive) output to the HDMI OUT B connector
R23
TX2_1–
O
TMDS data (negative) output to the HDMI OUT B connector
STR-DN850
75
Pin No.
Pin Name
I/O
Description
T1, T2
P[14], P[15]
I
Digital video signal input from the video A/D converter
T3, T4
GND
-
Ground terminal
T7 to T17
GND
-
Ground terminal
T20
HPD_TX2
I
Hot plug detection signal input from the HDMI OUT B connector
T21
GND
-
Ground terminal
T22
TX2_0+
O
TMDS data (positive) output to the HDMI OUT B connector
T23
TX2_0–
O
TMDS data (negative) output to the HDMI OUT B connector
U1, U2
P[10], P[11]
I
Digital video signal input from the video A/D converter
U3, U4
P[12], P[13]
I
Digital video signal input terminal Not used
U7, U8
GND
-
Ground terminal
U9
DVDD
-
Power supply terminal (+1.8V)
U10, U11
GND
-
Ground terminal
U12
DVDD
-
Power supply terminal (+1.8V)
U13, U14
GND
-
Ground terminal
U15
DVDD
-
Power supply terminal (+1.8V)
U16, U17
GND
-
Ground terminal
U20
R_TX2
-
External resistor connection terminal
U21
GND
-
Ground terminal
U22
TX2_C+
O
TMDS clock (positive) signal output to the HDMI OUT B connector
U23
TX2_C–
O
TMDS clock (negative) signal output to the HDMI OUT B connector
V1 to V4
P[6] to P[9]
I
Digital video signal input from the video A/D converter
V20
GND
-
Ground terminal
V21
PVDD4
-
Power supply terminal (+1.8V)
V22
HEAC_2+
I
HEAC (positive) signal input terminal Not used
V23
HEAC_2–
I
HEAC (negative) signal input terminal Not used
W1 to W4
P[2] to P[5]
I
Digital video signal input from the video A/D converter
W20
TEST3
-
Test terminal
W21
PVDD6
-
Power supply terminal (+1.8V)
W22
AVDD3
-
Power supply terminal (+1.8V)
W23
NC
-
Not used
Y1, Y2
P[0], P[1]
I
Digital video signal input terminal Not used
Y3
DDR_DQS[2]
O
Data strobe signal output to the SD-RAM
Y4
GND
-
Ground terminal
Y5
DDR_DQ[23]
I/O
Two-way data bus with the SD-RAM
Y6
DVDD_DDR
-
Power supply terminal (+1.8V)
Y7
DDR_DQS[3]
O
Data strobe signal output to the SD-RAM
Y8
GND
-
Ground terminal
Y9
DDR_A[11]
O
Address signal output to the SD-RAM
Y10
DVDD_DDR
-
Power supply terminal (+1.8V)
Y11
DDR_A[4]
O
Address signal output to the SD-RAM
Y12
GND
-
Ground terminal
Y13
DDR_/CAS
O
Column address strobe signal output to the SD-RAM
Y14
DVDD_DDR
-
Power supply terminal (+1.8V)
Y15
DDR_/CK
O
Clock signal output to the SD-RAM
Y16
GND
-
Ground terminal
Y17
DDR_DQ[9]
I/O
Two-way data bus with the SD-RAM
Y18
DVDD_DDR
-
Power supply terminal (+1.8V)
Y19
DDR_DQ[14]
I/O
Two-way data bus with the SD-RAM
Y20
GND
-
Ground terminal
Y21
DDR_DQ[6]
I/O
Two-way data bus with the SD-RAM
Y22
PVDD_DDR
-
Power supply terminal (+1.8V)
Y23
GND
-
Ground terminal
AA1
DDR_DQ[18]
I/O
Two-way data bus with the SD-RAM
AA2, AA3
GND
-
Ground terminal
AA4
DDR_/DQS[2]
O
Data strobe signal output to the SD-RAM
AA5
DDR_DQ[26]
I/O
Two-way data bus with the SD-RAM
STR-DN850
76
Pin No.
Pin Name
I/O
Description
AA6
DVDD_DDR
-
Power supply terminal (+1.8V)
AA7
DDR_/DQS[3]
O
Data strobe signal output to the SD-RAM
AA8
DDR_A[13]
O
Address signal output terminal Not used
AA9
DDR_A[8]
O
Address signal output to the SD-RAM
AA10
DVDD_DDR
-
Power supply terminal (+1.8V)
AA11
DDR_A[2]
O
Address signal output to the SD-RAM
AA12
GND
-
Ground terminal
AA13
DDR_/CS
O
Chip select signal output to the SD-RAM
AA14
DVDD_DDR
-
Power supply terminal (+1.8V)
AA15
DDR_CK
O
Clock signal output to the SD-RAM
AA16
GND
-
Ground terminal
AA17
DDR_DQ[11]
I/O
Two-way data bus with the SD-RAM
AA18
DVDD_DDR
-
Power supply terminal (+1.8V)
AA19,
AA20
DDR_DM[1],
DDR_DM[0]
O
Data mask signal output to the SD-RAM
AA21,
AA22
GND
-
Ground terminal
AA23
DDR_DQ[3]
I/O
Two-way data bus with the SD-RAM
AB1 to
AB3
DDR_DQ[21],
DDR_DQ[19],
DDR_DQ[19],
DDR_DQ[17]
I/O
Two-way data bus with the SD-RAM
AB4
DDR_DM[2]
O
Data mask signal output to the SD-RAM
AB5
DDR_DQ[30]
I/O
Two-way data bus with the SD-RAM
AB6
DDR_DM[3]
O
Data mask signal output to the SD-RAM
AB7, AB8
DDR_DQ[31],
DDR_DQ[29]
I/O
Two-way data bus with the SD-RAM
AB9 to
AB12
DDR_A[12], DDR_A[6],
DDR_A[3], DDR_A[0]
O
Address signal output to the SD-RAM
AB13
DDR_BA[0]
O
Bank address signal output to the SD-RAM
AB14
DDR_/RAS
O
Row address strobe signal output to the SD-RAM
AB15
DDR_CKE
O
Clock enable signal output to the SD-RAM
AB16
DDR_DQ[12]
I/O
Two-way data bus with the SD-RAM
AB17
DDR_DQS[1]
O
Data strobe signal output to the SD-RAM
AB18 to
AB21
DDR_DQ[8],
DDR_DQ[13],
DDR_DQ[0],
DDR_DQ[5]
I/O
Two-way data bus with the SD-RAM
AB22
DDR_DQS[0]
O
Data strobe signal output to the SD-RAM
AB23
DDR_DQ[4]
I/O
Two-way data bus with the SD-RAM
AC1 to
AC7
DDR_DQ[16],
DDR_DQ[20],
DDR_DQ[22],
DDR_DQ[25],
DDR_DQ[28],
DDR_DQ[27],
DDR_DQ[20],
DDR_DQ[22],
DDR_DQ[25],
DDR_DQ[28],
DDR_DQ[27],
DDR_DQ[24]
I/O
Two-way data bus with the SD-RAM
AC8 to
AC12
DDR_A[9], DDR_A[5],
DDR_A[7], DDR_A[1],
DDR_A[7], DDR_A[1],
DDR_A[10]
O
Address signal output to the SD-RAM
AC13,
AC14
DDR_BA[1],
DDR_BA[2]
O
Bank address signal output to the SD-RAM
AC15
DDR_/WE
O
Write enable signal output to the SD-RAM
AC16
DDR_VREF
O
Reference voltage output to the SD-RAM
AC17
DDR_DQ[10]
I/O
Two-way data bus with the SD-RAM
AC18
DDR_/DQS[1]
O
Data strobe signal output to the SD-RAM
AC19 to
AC21
DDR_DQ[15],
DDR_DQ[7],
DDR_DQ[2]
I/O
Two-way data bus with the SD-RAM
AC22
DDR_/DQS[0]
O
Data strobe signal output to the SD-RAM
AC23
DDR_DQ[1]
I/O
Two-way data bus with the SD-RAM
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