Sony STR-DN1010 Service Manual ▷ View online
STR-DN1010
65
Pin No.
Pin Name
I/O
Description
176 to
178
GPIO30 to GPIO32
-
Not used
179
VDD_HP_33
-
Power supply terminal (+3.3V)
180
AUD_HP_OUT_L
-
Not used
181
AUD_HP_OUT_R
-
Not used
182
GND_HP
-
Ground terminal
183
AUD_OUT2_L
-
Not used
184
AUD_OUT2_R
-
Not used
185
AUD_OUT1_L
-
Not used
186
AUD_OUT1_R
-
Not used
187
VDD_AUD1_33
-
Power supply terminal (+3.3V)
188
LS_OUT_L
-
Not used
189
LS_OUT_R
-
Not used
190
LS_OUT_SW
-
Not used
191
GND_AUD1
-
Ground terminal
192
VREFN
-
Ground terminal
193
VREFM
-
Not used
194
VREFP
-
Not used
195
VDD_AUD2_33
-
Power supply terminal (+3.3V)
196
AUD_IN_L4
-
Not used
197
AUD_IN_R4
-
Not used
198
AUD_IN_L3
-
Not used
199
AUD_IN_R3
-
Not used
200
AUD_IN_L2
-
Not used
201
AUD_IN_R2
-
Not used
202
AUD_IN_L1
-
Not used
203
AUD_IN_R1
-
Not used
204
AUD_MONO_IN
-
Not used
205
GND_AUD2
-
Not used
206
VDD_AUD_18
-
Power supply terminal (+1.8V)
207
GND_AUD_18
-
Ground terminal
208
VDD18_ABC_SC
-
Power supply terminal (+1.8V)
209
GND18_ABC_SC
-
Ground terminal
210
VDDA
-
Power supply terminal (+3.3V)
211
SIF_IN2
-
Not used
212
GNDA
-
Ground terminal
213
SIF_RTN
-
Not used
214
GNDA
-
Ground terminal
215
SIF_IN1
-
Not used
216
VDDA
-
Power supply terminal (+3.3V)
217
SV1P
-
Not used
218
VDDA
-
Power supply terminal (+3.3V)
219
A1P
I
Component video signal input from the video amplifi er
220
GNDA
-
Ground terminal
221
B1P
I
Component video signal input from the video amplifi er
222
GNDA
-
Ground terminal
223
C1P
I
Component video signal input from the video amplifi er
224
GNDA
-
Ground terminal
225
AN
-
Not used
226
GNDA
-
Ground terminal
227
SV2P
-
Not used
228
VDDA
-
Power supply terminal (+3.3V)
229
A2P
-
Not used
230
VDDA
-
Power supply terminal (+3.3V)
231
B2P
-
Not used
232
GNDA
-
Ground terminal
233
C2P
-
Not used
234
GNDA
-
Ground terminal
235
BN
-
Not used
236
GNDA
-
Ground terminal
STR-DN1010
66
Pin No.
Pin Name
I/O
Description
237
SV3P
-
Not used
238
VDDA
-
Power supply terminal (+3.3V)
239
A3P
-
Not used
240
VDDA
-
Power supply terminal (+3.3V)
241
B3P
-
Not used
242
GNDA
-
Ground terminal
243
C3P
-
Not used
244
GNDA
-
Ground terminal
245
CN
-
Not used
246
GNDA
-
Ground terminal
247
SV4P
I
Composite video signal input from the video amplifi er
248
GNDA
-
Ground terminal
249
A4P
-
Not used
250
GNDA
-
Ground terminal
251
B4P
-
Not used
252
GNDA
-
Ground terminal
253
C4P
-
Not used
254
VDDA
-
Power supply terminal (+3.3V)
255
SVN
-
Not used
256
VOUT2
-
Not used
STR-DN1010
67
DIGITAL VIDEO BOARD (4/5) IC3202 ABT1015LQ128 (VIDEO DEINTERLACING)
Pin No.
Pin Name
I/O
Description
1
RED[0]
O
Output red video data, not used
2
RED[1]
O
Output red video data, not used
3
RED[2]
O
Output red video data, not used
4
RED[3]
O
Output red video data, not used
5
PPL_VSS
-
PLL ground
6
PPL-VDD
-
PLL power supply (+1.8V)
7
SYSCLK
I
System clock input - 27MHz
8
IO_VDD
-
I/O Power supply (+3.3V)
9
IO_VSS
-
I/O ground
10
RED[9]
O
Output red video data, not used
11
RED[10]
O
Output red video data, not used
12
Core_VDD
-
Core power supply (+1.8V)
13
Core_VSS
-
Core ground
14
RED[11]
O
Output red video data, not used
15
BLUE[0]
O
Output blue video data, not used
16
BLUE[1]
O
Output blue video data, not used
17
BLUE[2]
O
Output blue video data, not used
18
BLUE[3]
O
Output blue video data, not used
19
BLUE[4]
O
Output blue video data, C[0]
20
BLUE[5]
O
Output blue video data, C[1]
21
BLUE[6]
O
Output blue video data, C[2]
22
BLUE[7]
O
Output blue video data, C[3]
23
BLUE[8]
O
Output blue video data, C[4]
24
BLUE[9]
O
Output blue video data, C[5]
25
BLUE[10]
O
Output blue video data, C[6]
26
BLUE[11]
O
Output blue video data, C[7]
27
Core_VDD
-
Core power supply (+1.8V)
28
Core_VSS
-
Core ground
29
IO_VDD
-
I/O Power supply (+3.3V)
30
IO_VSS
-
I/O ground
31
HSN
I/O
Output Hsync/also CSyncN. The state of this pin is latched during hardware reset-
Pull-Down - I2c device addr is 0x30
Pull-up - I2C device addr is 0x32
Input only used during reset
Pull-Down - I2c device addr is 0x30
Pull-up - I2C device addr is 0x32
Input only used during reset
32
VSN
I/O
Output Vsync.
The state of this pin is latched during hardware reset-
Pull-down - Use ABT1015’s internal PLL
Pull-up - Use external PLL to drive video output clock
Input only used during reset, function reserved
The state of this pin is latched during hardware reset-
Pull-down - Use ABT1015’s internal PLL
Pull-up - Use external PLL to drive video output clock
Input only used during reset, function reserved
33
IO_VDD
-
I/O Power supply (+3.3V)
34
IO_VSS
-
I/O ground
35
DE
I/O
Output Data Enable.
The state of this pin is latched during hardware reset-
- scaler VTG will start immediately after hardware reset
Pull-up - scaler VTG will be held in reset until released by software {reg. 0x848)
Input only used during reset.
The state of this pin is latched during hardware reset-
- scaler VTG will start immediately after hardware reset
Pull-up - scaler VTG will be held in reset until released by software {reg. 0x848)
Input only used during reset.
36
GREEN[0]
O
Output green video data, not used
37
GREEN[1]
O
Output green video data, not used
38
GREEN[2]
O
Output green video data, not used
39
GREEN[3]
O
Output green video data, not used
40
GREEN[4]
O
Output green video data, Y[0]
41
Core_VDD
-
Core power supply (+1.8V)
42
Core_VSS
-
Core ground
43
GREEN[5]
O
Output green video data, Y[1]
44
IO_VDD
-
I/O Power supply (+3.3V)
45
IO_VSS
-
I/O ground
46
GREEN[6]
O
Output green video data, Y[2]
47
GREEN[7]
O
Output green video data, Y[3]
STR-DN1010
68
Pin No.
Pin Name
I/O
Description
48
GREEN[8]
O
Output green video data, Y[4]
49
GREEN[9]
O
Output green video data, Y[5]
50
GREEN[10]
O
Output green video data, Y[6]
51
GREEN[11]
O
Output green video data, Y[7]
52
INVOUTCLK
I
Reference clock for the video output clock.
Pull-up or pull-down if not used
Pull-up or pull-down if not used
53
Core_VDD
-
Core power supply (+1.8V)
54
Core_VSS
-
Core ground
55
VOUTCLK
O
Output video clock
56
PLL_VSS
-
PLL ground
57
PLL_VDD
-
PLL power supply (+1.8V)
58
IO_VDD
-
I/O Power supply (+3.3V)
59
IO_VSS
-
I/O ground
60
INPUTVCLK
I
Input video clock
61
SDA
I/O
Serial data. Output is open drain
62
SCL
I
Serial clock
63
RESETN
I
Chip reset
64
Core_VDD
-
Core power supply (+1.8V)
65
Core_VSS
-
Core ground
66
INPUTDE
I
Input data enable
67
INPUTHSN
I
Input horizontal sync
68
INPUTVSN
I
Input vertical sync
69
Core_VDD
-
Core power supply (+1.8V)
70
Core_VSS
-
Core ground
71
INPUTCB[0]
I
Cb video input data, not used
72
INOUTCB[1]
I
Cb video input data, not used
73
IO_VDD
-
I/O Power supply (+3.3V)
74
IO_VSS
-
I/O ground
75
INPUTCB[2]
I
Cb video input data, not used
76
INPUTCB[3]
I
Cb video input data, not used
77
INPUTCB[4]
I
Cb video input data, CB[0]
78
INPUTCB[5]
I
Cb video input data, CB[1]
79
INOUTCB[6]
I
Cb video input data, CB[2]
80
INOUTCB[7]
I
Cb video input data, CB[3]
81
INPUTCB[8]
I
Cb video input data, CB[4]
82
INPUTCB[9]
I
Cb video input data, CB[5]
83
INOUTCB[10]
I
Cb video input data, CB[6]
84
INPUTCB[11]
I
Cb video input data, CB[7]
85
INOUTY[0]
I
Luma video input data, not used
86
INDUTY[1]
I
Luma video input data, not used
87
INPUTY[2]
I
Luma video input data, not used
88
INPUTY[3]
I
Luma video input data, not used
89
INPUTY[4]
I
Luma video input data, Y[0]
90
IO_VDD
-
I/O Power supply (+3.3V)
91
IO_VSS
-
I/O ground
92
INPUTY[5]
I
Luma video input data, Y[1]
93
INPUTY[6]
I
Luma video input data, Y[2]
94
INPUTY[7]
I
Luma video input data, Y[3]
95
Core_VDD
-
Core power supply (+1.8V)
96
Core_VSS
-
Core ground
97
INPUTY[8]
I
Luma video input data, Y[4]
98
INPUTY[9]
I
Luma video input data, Y[5]
99
INPUTY[10]
I
Luma video input data, Y[6]
100
INPUTY[11]
I
Luma video input data, Y[7]
101
IO_VSS
-
I/O ground
102
IO_VDD
-
I/O Power supply (+3.3V)
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