Sony STR-DG500 Service Manual ▷ View online
45
STR-DG500
• DESCRIÇÕES DOS PINOS DE IC
IC1501 CXD9718BQ (DSP) (Placa DIGITAL (2/5))
Pin No.
Pin Name
I/O
Pin Description
1
VSS
—
Ground
2
XRST
I
Reset signal input from SYSTEM CONTROL IC
3
EXTIN
I
Not used (Connect to ground)
4
LRCKI3
I
Not used (Connect to ground)
5
VDDI
I
Power supply pin (+2.6 V)
6
BCKI3
I
Not used (Connect to ground)
7
PLOCK
O
Not used (Open)
8
VSS
—
Ground
9
MCLK1
I
Clock signal input (13.9 MHz)
10
VDDI
I
Power supply pin (+2.6 V)
11
VSS
—
Ground
12
MCLK2
O
Clock signal output (13.9 MHz)
13
MS
I
Not used (Fixed at L)
14
SCKOUT
O
Internal system clock signal output for 8CH DAC IC
15
LRCKI1
I
Sampling clock signal input from ADC IC
16
VDDE
I
Power supply pin (+3.3 V)
17
BCKI1
I
Bit clock signal input from ADC IC
18
SDI1
I
Audio IF data input from ADC IC
19
LRCKO
O
Sampling clock signal output for 8CH DAC IC
20
BCKO
O
Bit clock signal output for 8CH DAC IC
21
VSS
—
Ground
22
KFSIO
I/O
Audio clock signal (384fs/256fs) input/output for DIR IC
23 to 26
SDO1 to SDO4
O
Digital audio serial data output for 8CH DAC IC
27
SPDIF
O
Not used (Open)
28
LRCKI2
I
Sampling clock signal input from ADC IC
29
BCKI2
I
Bit clock signal input from ADC IC
30
SDI2
I
Digital audio serial data input from ADC IC
31
VSS
—
Ground
32
HACN
O
Acknowledge signal output for SYSTEM CONTROL IC
33
HDIN
I
Serial data input from SYSTEM CONTROL IC
34
HCLK
I
Clock signal input from SYSTEM CONTROL IC
35
HDOUT
O
Serial data output for SYSTEM CONTROL IC
36
HCS
I
Chip select signal input from SYSTEM CONTROL IC
37
GP12
I
GP12 signal input from SYSTEM CONTROL IC
38, 39
GP13, GP14
O
Not used (Open)
40
VDDI
I
Power supply pin (+2.6 V)
41
VSS
—
Ground
42
GP15
O
Not used (Open)
43
OE0
O
Not used (Open)
44
CS0
O
External memory chip select signal output for D/A converter IC (SDRAM)
45
WE0
O
SDRAM write enable signal output for D/A converter IC (SDRAM)
46
VDDE
I
Power supply pin (+3.3 V)
47
WMD1
I
Not used (Fixed at H)
48
VSS
—
Ground
49
WMD0
I
Not used (Fixed at H)
50
PAGE2
O
Not used (Open)
51
VSS
—
Ground
52, 53
PAGE1, PAGE0
O
Not used (Open)
54
BOOT
I
Not used (Connect to ground)
55
TST1
O
Not used (Open)
56
BST
I
Boot stop signal input from SYSTEM CONTROL IC
46
STR-DG500
Pin No.
Pin Name
I/O
Pin Description
57
MOD1
I
Operation mode signal input (L: 386fs, H: 256fs) (Fixed at H)
58
MOD0
I
Operation mode signal input (L: single chip mode, H: use prohibited) (Fixed at L)
59
EXLOCK
I
Error detection signal input from DIR IC
60
VDDI
I
Power supply pin (+2.6 V)
61
VSS
—
Ground
62, 63
A17, A16
O
Not used (Open)
64 to 66
A15 to A13
O
External memory address signal output for D/A converter IC (SDRAM)
67
GP10
O
Not used (Open)
68
GP9
O
GP9 signal output for SYSTEM CONTROL IC
69
GP8
I
Audio signal input from DIR IC
70
VDDI
I
Power supply pin (+2.6 V)
71
VSS
—
Ground
72 to 75
D15/GP7 to D12/GP4
I/O
External memory data input/output for D/A converter IC (general port)
76
VDDE
I
Power supply pin (+3.3 V)
77 to 80
D11/GP3 to D8/GP0
I/O
External memory data input/output for D/A converter IC (general port)
81
VSS
—
Ground
82
A9
O
External memory address signal output for D/A converter IC (SDRAM)
83 to 85
A12 to A10
O
External memory address signal output for D/A converter IC (SDRAM)
86
TDO
O
Not used (Fixed at H)
87
TMS
I
Not used (Fixed at H)
88
XTRST
I
Not used (Fixed at H)
89
TCK
I
Not used (Fixed at H)
90
TDI
I
Not used (Fixed at H)
91
VSS
—
Ground
92 to 97
A8 to A3
O
External memory address signal output for D/A converter IC (SDRAM)
98, 99
D7, D6
I/O
External memory data input/output for D/A converter IC (SDRAM)
100
VDDI
I
Power supply pin (+2.6 V)
101
VSS
—
Ground
102 to 105
D5 to D2
I/O
External memory data input/output for D/A converter IC (SDRAM)
106
VDDE
I
Power supply pin (+3.3 V)
107, 108
D1, D0
I/O
External memory data input/output for D/A converter IC (SDRAM)
109, 110
A2, A1
O
External memory address signal output for D/A converter IC (SDRAM)
111
VSS
—
Ground
112
A0
O
External memory address signal output for D/A converter IC (SDRAM)
113
PM
I
PLL initialization signal input from SYSTEM CONTROL IC
114, 115
SDI3, SDI4
I
Not used (Open)
116
SYNC
I
Sync/async select signal input (L: sync, H: async) (Fixed at H)
117
TST2
I
Not used (Connect to ground)
118
GP11
I
Not used (Connect to ground)
119
TST3
I
Not used (Connect to ground)
120
VDDI
I
Power supply pin (+2.6 V)
47
STR-DG500
IC1101 MB90488BPF-G-175E1 (SYSTEM CONTROL) (DIGITAL BOARD (5/5))
Pin No.
Pin Name
I/O
Pin Description
1
DATAO
I
Serial data line signal input from DIR IC
2
GP9
I
GP9 signal input from DSP IC
3
BST
O
Boot stop control signal output for DSP IC
4
HCS
O
Chip select signal output for DSP IC
5
HACN
I
Acknowledge signal input from DSP IC
6
XRST
O
Reset signal output for DSP IC
7
PM
O
PLL control signal output for DSP IC
8
GP12
O
GP12 signal output for DSP IC
9
FL_LAT
O
Latch signal output for FL driver IC
10
PCM1609/1800_RST
O
Reset signal output for 8CH DAC IC/ADC IC
11
VSS
—
Ground
12
PCM1609_ML
O
Serial latch signal output for 8CH DAC IC
13
PCM1609_MC/
O
Serial clock signal output for 8CH DAC IC/XM DIGITAL TRANSCEIVER IC
XMDACMC
(STR-DG600)
14
PCM1609_MDI/XMDACMI
O
Serial data output for 8CH DAC IC/XM DIGITAL TRANSCEIVER IC (STR-DG600)
15
PCM1609_MDO
I
Serial data input from 8CH DAC IC
16
T.SERIAL_CLK/FL_CLK
O
Serial clock signal output for tuner pack/Clock signal output for FL driver IC
17
TUNER_DATA/FL_DATA
O
Serial data output for tuner pack/Serial data output for FL driver IC
18
HDOUT
I
Serial data input from DSP IC
19
HDIN
O
Serial data output for DSP IC
20
HCLK
O
Serial data clock signal output for DSP IC
21
TUNING_A
I
TUNING +/– encoder (A) signal input (STR-DG600)
22
TUNING_B
I
TUNING +/– encoder (B) signal input (STR-DG600)
23
VCC5
—
Power supply pin (+3.3 V)
24
FL_RESET (DE8)
O
Not used (Fixed at L)
25
ANA/DIG
O
Not used (Open)
26
XM_RST
O
XM radio reset signal output (STR-DG600)
27
FLASH2/XM_RX
I
Flash programming signal input 2/XM radio RX signal input (STR-DG600)
28
FLASH1/XM_TX
O
Flash programming signal output 1/XM radio TX signal output (STR-DG600)
29
SDA
I/O
Serial data input/output for EEPROM IC
30
SCL
O
Clock signal output for EEPROM IC
31
ENC_A
I
INPUT SELECTOR encoder (A) signal input
32
ENC_B
I
INPUT SELECTOR encoder (B) signal input
33
UPCON
I/O
Serial data input/output for Y/C SEPARATION IC (STR-DG600)
34
UPCON_CLK
O
Clock signal output for Y/C SEPARATION IC (STR-DG600)
35
AVCC
—
Power supply pin (+3.3 V)
36
AVRH
—
Power supply pin (+3.3 V)
37
AVSS
—
Ground
38
ADCC
I
ADCC analog signal input
39, 40
A/D1, A/D2
I
Key signal input (A/D port)
41
VERSION
I
Destination detection signal input
42
VSS
—
Ground
43
RDSSIG/XM_REQ
I/O
RDS signal level input (AEP, UK model)/XM radio request signal input (STR-DG600)
44
MODEL/CSMUTE (E8)
I/O
Model detection signal input
45
TONE_EN_B (E8)/VACS
I
Not used (Fixed at L)
46
TONE_EN_A (E8)
I
Not used (Fixed at L)
47
XMDACMS
O
Serial latch signal output for XM DIGITAL TRANSCEIVER IC (STR-DG600)
48
STOP
I
AC off detection signal input
49
MD0
—
Selection of micon operation mode
50
MD1
—
Not used (Connect to VCC)
51
MD2
—
Selection of micon operation mode
48
STR-DG500
Pin No.
Pin Name
I/O
Pin Description
52
RDS_CLK/XMDPOWER
I/O
RDS data clock signal input (AEP, UK model)/XM digital power control signal output
(STR-DG600)
53
RDS_DATA/
I/O
RDS data input (AEP, UK model)/XM command control signal output (STR-DG600)
XM_COMMAND
54
SIRCS
I
SIRCS signal input
55
HP_DETECT
I
Headphones detection signal input
56
POWER_KEY
I
Power key detection signal input
57
ADCC_INT
I
ADCC data input from DSP IC
58
POWER_RY
O
Power relay driver control signal output
59
VOL_CL
O
Clock signal output for DIR IC
60
VOL_DA
O
Serial data and latch output for DIR IC
61
PROTECTOR
I
Protector detection signal input
62
HP_RY
O
Headphone relay driver control signal output
63
FUSE_DETECT
I
Fuse open detection signal input
64
VOL_ENCODER (B)
I
MASTER VOLUME encoder (B) signal input
65
VOL_ENCODER (A)
I
MASTER VOLUME encoder (A) signal input
66
FRONT_RY
O
Front speaker relay driver control signal output
67
SP_B_RY
O
Front speaker B relay driver control signal output
68
C/SB_RY
O
Center/Surround back speaker relay driver control signal output
69
REAR_RY
O
Surround speaker relay driver control signal output
70
SW_RY
O
Sub woofer relay driver control signal output
71
ANALOG_SW_CLK (DE8)
O
Not used (Open)
72
BRIDGEABLE_RY
O
Bridgeable relay driver control signal output
73
DO
I
Tuner serial data input
74
SLATCH
O
Tuner latch signal output
75
TUNED
I
Tuned signal detection input
76
STEREO
I
Stereo signal detection input
77
RSTX
I
Reset signal input
78
MUTE
O
Tuner mute signal output
79
X1A
—
Not used (Open)
80
X0A
—
Not used (Connect to VSS)
81
VSS
—
Ground
82
X0
—
Clock signal input (24 MHz)
83
X1
—
Clock signal output (24 MHz)
84
VCC3
—
Power supply pin (+3.3 V)
85
ANALOG_SW_DATA
O
Not used (Open)
(DE8)
86
D595_DATA
O
Serial data output for I/O EXPANDER IC
87
D595_CLK
O
Serial clock signal output for I/O EXPANDER IC
88
D595_OE
O
Serial output enable signal output for I/O EXPANDER IC
89
D595_LAT
O
Serial latch signal output for I/O EXPANDER IC
90
SELECT2
O
Digital input select 2 signal output (STR-DG600)
91
SELECT1
O
Digital input select 1 signal output (STR-DG600)
92
BST_SEL
O
96/24 signal output for DSP IC
93
XMODE
O
Xmode signal output for DIR IC
94
CKSEL1
O
Clock select signal output for DIR IC
95
CLK
O
Data clock signal output for DIR IC
96
CE
O
Latch signal output for DIR IC
97
DI
O
Data output for DIR IC
98
DO
I
Data input from DIR IC
99
ERROR
I
Error detection signal input from DIR IC
100
XSTATE
I
Xstate signal input from DIR IC
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