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SDTO source select pin

“L”: internal ADC output, “H”: DAUX input

ORed with serial control register if P/S = “L” (Connected to GND)

MCKO clock frequency select pin

“L”: MCLK, “H”: MCLK/2.  ORed with serial control register if P/S = “L” (Connected to GND)

Audio data master/slave mode select pin

“L”: slave mode, “H”: master mode (Connected to GND)

Audio serial data clock pin

Input/output channel clock pin

DAC1 audio serial data input pin

DAC2 audio serial data input pin

DAC3 audio serial data input pin

Audio serial data output pin

AUX audio serial data input pin (Connected to GND)

Double speed sampling mode pin

“L”: normal speed, “H”: double speed

ORed with serial control register if P/S = “L” (Connected to GND)

De-emphasis pin

ORed with serial control register if P/S = “L” (Connected to GND)

Master clock output pin (Not used)

Digital power supply pin

Digital ground pin

Power-down & reset pin

When “L”, the AK4526 is powered-down and the control registers are reset to default state.

If the state of P/S, M/S, CAD0-1 changes, then the AK4526 must be reset by PD.

X’tal oscillator select/test mode pin

“H”: X’tal oscillator selected

“L”: External clock source selected

“NC”: If pin is floating then test mode is enabled. (Connected to GND)

Input clock select 1 pin (Connected to GND)

Input clock select 0 pin (Connected to GND)

Chip address pin

Used during the serial control mode. (Connected to GND)

Chip address pin

Used during the serial control mode. (Connected to GND)

Lch #3 analog output pin

Rch #3 analog output pin

Lch #2 analog output pin

Rch #2 analog output pin

Lch #1 analog output pin

Rch #1 analog output pin

Lch analog negative input pin

Lch analog positive input pin

SDOS

MCLK

S/M

BCLK

LRCK

SDT11

SDT12

SDT13

SDTO

DAUX

DFS

DEM1 – DEM0

MCKO

D. 5V

D. GND

PD

TEST

ICKS1

ICKS0

CAD1

CAD0

LOUT3

ROUT3

LOUT2

ROUT2

LOUT1

ROUT1

LIN–

LIN+

1

2

3

4

5

6

7

8

9

10

11

12 – 13

14

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16

17

18

19

20

21

22

23

24

25

26

27

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29

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Rch analog negative input pin

Rch analog positive input pin

Negative voltage reference input pin, AVSS (Connected to GND)

Common voltage output pin,  AVDD/2

 Large external capacitor is used to reduce power-supply noise

Positive voltage reference input pin, AVDD

Analog power supply pin

Analog ground pin

X’tal input pin (Not used)

External master clock input pin if XTS = “L”

Parallel/serial select pin

“L”: serial control mode, “H”: parallel control mode (Connected to GND)

Chip select pin in serial mode

Control data clock pin in serial mode

Control data input in serial mode

Control data output pin in serial mode

RIN–

RIN+

VREFL

VCOM

VREFH

A. 5V

A. GND

XTI

MCLKI

S/P

CS

CCLK

CDTI

CDTO

If pins TEST, ICKS0, ICKS1, PD, S/P, DFS, DEM0, DEM1, CAD0, CAD1, S/M, MCLK, SDOS are not driven, then TEST, ICKS0, ICKS1, CAD0, CAD1,
must be tied to either AVSS or AVDD. PD, S/P, DFS, DEM0, DEM1, S/M, MCLK, SDOS must be tied to either DVSS or DVDD.

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2 – 5

6, 7

8

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16 – 20

21

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23 – 25

26

27 – 30

31

32 – 40

41

42

43 – 49

50

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52

53 – 60

61

62 – 69

70

71

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73

74

75

76 – 80

81

82

83 –89

90

—

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NC

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GND

Serial data output

Conditional jump input terminal (7pin Connected to GND)

No connection

HCIF data write

HCIF data read

GND

+3.3V

HCIF ready signal  Open drain

HCIF chip select

HCIF address input

HCIF data input/output

GND

+3.3V

HCIF data input/output

Reset input  “L”: active

Test data output

GND

External RAM data input/output

GND

+3.3V

External RAM data input/output

Test data input  “L” = normal  “H” = test (Connected to GND)

GND

+3.3V

External RAM data input/output

GND

External RAM data input/output

External RAM output enable

GND

+3.3V

External RAM column address strobe (Not used)

External RAM write enable (Not used)

External RAM raw address strobe

External RAM address output/test data input

GND

+3.3V

External RAM address output/test data input

External RAM address output

VSS3

SOA – SOD

ECJ0, ECJ1

—

XHDWR

XHDRD

V

SS

4

V

DD

2

HRDY

XHDCS

HA0

HD0 – HD4

V

SS

5

V

DD

3

HD5 – HD7

XRST

FGP0 – FGP3

V

SS

6

ED0 – ED8

V

SS

7

V

DD

4

ED9 – ED15

TSTD

V

SS

8

V

DD

5

ED16 – ED23

V

SS

9

ED24 – ED31

XOE

V

SS

10

V

DD

6

CAS

XWE

RAS

EA0 – EA4

V

SS

11

V

DD

7

EA5  – EA11

EA12

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117 – 120

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GND

External RAM address output

Not used

Test data input  “L” = normal  “H” = test (Connecting to GND)

PLL input frequency select  “L” = 256Fs  “H” = 128Fs (Connecting to GND)

PLL output frequency select  “L” = 768Fs  “H” = 1024Fs (Connecting to GND)

Master clock input

Master clock output (Not used)

GND

+3.3V

GND for PLL cell

VDD for PLL cell

PLL output/test clock input

PLL cell oscillation enable  “L” oscillation enable  “H” oscillation stop (Connecting to GND)

Test data input  “L” = normal  “H” = test (Connecting to GND)

Frequency counter input (Connecting to GND)

LRCK0 divider output

BCK0 divider output

GND

+3.3V

BCK input

BCK input

LRCK input

LRCK input

Serial data input

V

SS

0

EA13 – EA15

EA16

TSTA

PLDIVF

PLDIVB

CLKI

CLKO

V

SS

1

V

DD

0

AV

SS

AV

DD

PLLCK

XPLLEN

TST

LRCT

LROUT

BKOUT

V

SS

2

V

DD

1

BCK0

BCK1

LRCK0

LRCK1

SIA – SID