Sony STR-DE635 Service Manual ▷ View online
STR-DE635
— 45 —
— 46 —
4-20.
SCHEMATIC DIAGRAM MAIN SECTION(1/2)
• See page 61 for IC Block Diagrams.
STR-DE635
—47 —
— 48 —
4-21.
SCHEMATIC DIAGRAM MAIN SECTION (2/2)
• See page 43 for Printed Wiring Board. • See page 61 for IC Block Diagrams.
The components identified by
mark
mark
!
or dotted line with mark
!
are critical for safety.
Replace only with part number
specified.
specified.
Les composants identifiés par
une marque
une marque
!
sont critiques
pour la sécurité.
Ne les remplacer que par une
pièce portant le numéro spécifié.
Ne les remplacer que par une
pièce portant le numéro spécifié.
— 49 —
4-22.
IC PIN FUNCTION DESCRIPTION
IC1401
CXD2712R AUDIO DSP(DIGITAL BOARD)
Pin No.
1
2 – 5
6, 7
8
9
10
11
12
13
14
15
16 – 20
21
22
23 – 25
26
27 – 30
31
32 – 40
41
42
43 – 49
50
51
52
53 – 60
61
62 – 69
70
71
72
73
74
75
76 – 80
81
82
83 –89
90
I/O
—
O
I
NC
I
I
—
—
O
I
I
I/O
—
—
I/O
I
O
—
I/O
—
—
I/O
I
—
—
I/O
—
I/O
O
—
—
O
O
O
I/O
—
—
I/O
O
Description
Ground
Serial data output
Conditional jump input terminal (7pin Connected to ground)
No connection
HCIF data write
HCIF data read
Ground
+3.3V
HCIF ready signal Open drain
HCIF chip select
HCIF address input
HCIF data input/output
Ground
+3.3V
HCIF data input/output
Reset input “L”: active
Test data output
Ground
External RAM data input/output
Ground
+3.3V
External RAM data input/output
Test data input “L” = normal “H” = test (Connected to ground)
Ground
+3.3V
External RAM data input/output
Ground
External RAM data input/output
External RAM output enable
Ground
+3.3V
External RAM column address strobe (Not used)
External RAM write enable (Not used)
External RAM raw address strobe
External RAM address output/test data input
Ground
+3.3V
External RAM address output/test data input
External RAM address output
Pin Name
VSS3
SOA – SOD
ECJ0, ECJ1
—
XHDWR
XHDRD
V
SS
4
V
DD
2
HRDY
XHDCS
HA0
HD0 – HD4
V
SS
5
V
DD
3
HD5 – HD7
XRST
FGP0 – FGP3
V
SS
6
ED0 – ED8
V
SS
7
V
DD
4
ED9 – ED15
TSTD
V
SS
8
V
DD
5
ED16 – ED23
V
SS
9
ED24 – ED31
XOE
V
SS
10
V
DD
6
CAS
XWE
RAS
EA0 – EA4
V
SS
11
V
DD
7
EA5 – EA11
EA12
— 50 —
Pin No.
91
92 – 94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117 – 120
I/O
—
O
O
I
I
O
I
O
—
—
—
—
I/O
I
I
I
O
O
—
—
I
I
I
I
I
Description
Ground
External RAM address output
Not used
Test data input “L” = normal “H” = test (Connecting to ground)
PLL input frequency select “L” = 256Fs “H” = 128Fs (Connecting to ground)
PLL output frequency select “L” = 768Fs “H” = 1024Fs (Connecting to ground)
Master clock input
Master clock output (Not used)
Ground
+3.3V
Ground for PLL cell
VDD for PLL cell
PLL output/test clock input
PLL cell oscillation enable “L” oscillation enable “H” oscillation stop (Connecting to ground)
Test data input “L” = normal “H” = test (Connecting to ground)
Frequency counter input (Connecting to ground)
LRCK0 divider output
BCK0 divider output
Ground
+3.3V
BCK input
BCK input
LRCK input
LRCK input
Serial data input
Pin Name
V
SS
0
EA13 – EA15
EA16
TSTA
PLDIVF
PLDIVB
CLKI
CLKO
V
SS
1
V
DD
0
AV
SS
AV
DD
PLLCK
XPLLEN
TST
LRCT
LROUT
BKOUT
V
SS
2
V
DD
1
BCK0
BCK1
LRCK0
LRCK1
SIA – SID
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