Sony STR-DE235 Service Manual ▷ View online
STR-DE235
– 29 –
– 30 –
4-12. SCHEMATIC DIAGRAM – PANEL Section –
•
See page 20 for Waveform.
•
See page 35 for IC Block Diagram.
(Page 23)
(Page 32)
STR-DE235
– 31 –
– 32 –
4-13. PRINTED WIRING BOARDS – VOLUME Board/TONE Board –
•
•
See page 14 for Circuit Boards Location.
4-14.
SCHEMATIC DIAGRAM – VOLUME Board/TONE Board –
(Page 15)
(Page 15)
(Page 27)
(Page 29)
(Page 23)
(Page 19)
– 33 –
• IC Block Diagrams
– MAIN BOARD –
– MAIN BOARD –
IC1
BU1924
IC300
CXA8079S
QUALITY BIT
GENERATOR
DEFFERENTIAL
DECODER
BIPHASE
SYMBOL
SYMBOL
DECODER
OSCILLATOR
AND
DIVIDER
57kHz
BANDPASS
(8th ORDER)
CONTAS LOOP
VARIABLE AND
FIXED DIVIDER
FIXED DIVIDER
REFERENCE
VOLTAGE
ANTI-
ALIASING
FILTER
CLOCKED
COMPARATOR
TEST LOGIC AND OUTPUT
SELECTOR SWITCH
RECONSTRUCTION
FILTER
14
15
16
13
12
11
10
9
3
2
1
4
5
6
7
8
CLOCK REGENERATION
AND SYNC
VP1
RDCL
TS7
OSCO
OSCI
V
DDD
V
SSD
TEST
TSTL
D
QUAL
RDDA
Vref
MUX
V
DDA
V
SSA
CIN
SCOUT
48
VCS2
VCS1
VCS-TH
L+R-RCT
L-R-RCT
DCUT
DCUT
R-BPF3
R-BPF2
R-BPF1
CT
-OUT2
CT
-IN2
MIXOUT
C-OUT
S-OUT
R-OUT
L-OUT
VCC
CM-CAP
FCC-IN2
ENABLE
D
ATA
CLK
OSC1
NS-BPF1
NS-BPF2
VREF
S-DCUT
C-DCUT
L-DCUT
R-DCUT
VREF-BUF
L-IN
R-IN
GND
CT
-OUT1
CT
-IN1
FCC-IN1
L-BPF1
L-BPF2
L-BPF3
DCUT
DCUT
R-RCT
L-RCT
VLR-TH
VLR1
VLR2
47 46 45
44 43
42
41
40
39
38
37
36
35
34
33
32
31
30 29 28
L+R-RECT
27
26
25
P.S
VCS-LOG
OSC
DEC
N-GEN
N-BPF
N-OH
DIV
BAL-DET
BALCONT
VREF
VR
VR
VCRX8
COMB-NET
CMODE
SMUTE
C-TRIM
P
B
P
B
P
B
P
B
R
B
R
B
R-B.P.F.
L-B.P.F.
L-R-RECT
R-RECT
L-RECT
VLR-LOG
DUAL-TIME
P.S
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
– 34 –
IC301
LV1018
IC401
LC78212
IC701, 702
µPC2581V
VSS
CLK
D
ATA
ENABLE
LS-DC CUT
LS-DC CUT
DC CUT
-IN
VCC
L-IN
R-IN
S-IN
AC-GND
NR-C2
FCL-IN
FCR-IN
FCLS-IN
FCRS-IN
DELA
Y
-OUT
DELA
Y
-IN
CR-IN
CR-OUT
LC-INE
LC-INB
RS-DC CUT
RS-DC CUT
AGND
DC-OUT
IREF
DET
LPF
L-OUT
R-OUT
LS-OUT
RS-OUT
VDD
A/D
NS
D/A
1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
21
22
23
24
25
37 36 35
40
41
42
39
38
34 33 32 31 30 29 28 27 26
LS
TRIM
FILTER
B-NR
VDD
PCM
DATA
DECODER
OSC
PCM
CONTROL
8K-SRAM
FILTER
VOLUME
FILTER
R-STEREO
RS
TRIM
+
–
+
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CONTROL
LATCH
SHIFT RESISTOR
LEVEL SHIFT
CL
DI
CE
VEE
OUT
IN
OUT
IN
OUT
IN
VSS
S
RESET
VDD
OUT
IN
IN
OUT
IN
OUT
IN
2
3
5
4
6
7
9
8
1
MUTE
+ VOUT1
– VOUT1
COMP1
MF1
IN1
GND
IN2
NF2
COMP2
– VOUT2
+ VOUT2
VCC1
VCC2
VEE
PROTECTOR
BIAS CIRCUIT
REG
DRIVE
PRE
DRIVE
11
10
12
13
15
14
DRIVE
PRE
DRIVE
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