DOWNLOAD Sony STR-DA7100ES Service Manual ↓ Size: 52.09 MB | Pages: 127 in PDF or view online for FREE

Model
STR-DA7100ES
Pages
127
Size
52.09 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
str-da7100es.pdf
Date
PREV: Sony DAV-DZ770W / DAV-FX999W / TA-WR3 Service Manual

Sony STR-DA7100ES Service Manual ▷ View online

93
93
STR-DA7100ES
STR-DA7100ES
• See page 148, 149 for IC Block Diagrams.
6-33. SCHEMATIC  DIAGRAM  – ILINK SECTION (2/10) –
R3162
R3161
R3160
C3094
C3093
C3092
C3095
CN3003
C3068
FB3008
R3121
R3144
R3142
FB3003
R3115
C3057
C3061
C3056
IC3012
C3052
C3075
C3083
C3060
C3067
C3064
R3136
R
3
1
1
4
R
3
1
1
6
R
3
1
1
7
R
3
1
1
9
R
3
1
2
0
C
3
0
5
8
C
3
0
6
2
C3066
R3124
R3126
C3050
C3055
IC3015
C3078
C3082
R3159
R3155
R3130
R3112
R3151
R3125
C3063
IC3011
R3152
R3158
C3072
IC3013
IC3017
IC3010
IC3009
IC3007
R3138
C3049
R3118
CN3004
FB3007
D3006
FB3004
IC3008
R3146
R3149
CNP302
CNR208
CNP301
CNR207
100
100
100
0.1
100
10V
470
10V
0.1
20P
0.1
47
0
47
1k
0.1
0.1
0.1
TC7WH74FU
0.1
0.1
47
10V
0.1
0.1
0.1
10k
1
0
0
1
0
0
1
0
0
1
0
0
4
7
0
.1
0
.1
1000
10V
10k
10k
0.1
0.1
NJM2391DL-26
1000
10V
0.1
100
100
47
100
100
1k
0.01
CXD9850Q
100
100
0.1
74VHC157FT
BA33BC0FP-E2
TC74VHC04FT
74VHC157FT
SN74AHC2G157HDCT
100
0.1
10k
16P
1SR154
SN74AHC1G08DCKR
0
0
16P
16P
20P
20P
C
1
C
5
C
2
C
3
C
4
C
6
C
7
C
8
C
9
C
1
0
C
1
1
C
1
2
C13
C14
C15
C16
C17
C
1
8
C
1
9
C
2
0
C
2
2
C
2
3
C
2
4
C
2
5
D1
D2
D3
D4
D5
D6
D7
GND
HRESET
HUART_RX
HUART_TX
MCKO
BCKO
LRCKO
SPDIF
SD0
SD1
SD2
MUTEOUT
H5.6V
22MHZ
24MHZ
SPDIF
MCK
LRCK
BCK
DATA1
DATA2
DATA3
DATA4
ERROR
9742-INIT
9742-FS
(2/10)
DIGITAL AUDIO
PROCESSOR
+2.6V REGULATOR
O
G
I
DATA SELECTOR
DATA SELECTOR
CLOCK SWITCH
CLOCK DIVIDER
INVERTER
+3.3V REGULATOR
DATA SELECTOR
O
G
I
TEMP
TEMP
MCK-SW
24 OFF
22 OFF
I/H_SEL
TEMP
TEMP
9742-FS
9742-INT
I/H-SEL
ERROR
SPDIF
DATA4
DATA3
DATA2
DATA1
BCK
LRCK
MCK-SW
MCK
24OFF
24MHZ
22OFF
22MHZ
TEMP
TEMP
9742-FS
9742-INT
I/H-SEL
ERROR
SPDIF
DATA4
DATA3
DATA2
DATA1
BCK
LRCK
MCK-SW
MCK
24OFF
24MHZ
22OFF
22MHZ
H-RESET
H-UART-RX
H-UART-TX
I-RESET
RTS
CTS
I-UART-RX
I-UART-TX
I+5V
H+5V
DGND
I+5V
ILINKGND
ILINKGND
H+5V
D+3.3V
I-UART-TX
I-UART-RX
CTS
RTS
I-RESET
H-UART-TX
H-UART-RX
H-RESET
ILINKGND
ILINKGND
I+5V
I+5V
H+5V
H+5V
DGND
D+3.3V
I-UART-TX
I-UART-RX
CTS
RTS
I-RESET
H-UART-TX
H-UART-RX
H-RESET
ILINKGND
ILINKGND
I+5V
I+5V
H+5V
H+5V
DGND
D+3.3V
(Page 92)
(Page 95)
(Page 92)
(Page 95)
(Page 95)
(Page 95)
(Page 95)
(Page 96)
(Page 98)
(Page 97)
(Page 116)
(Page 116)
94
94
STR-DA7100ES
STR-DA7100ES
• See page 44 for IC Pin Function Description.
6-34. SCHEMATIC  DIAGRAM  – ILINK SECTION (3/10) –
C3024
C3037
R3006
R3038
R3039
R3040
R3096
R3097
R3098
C3019
R3087
R3085
R3083
R3082
R3081
R3080
C3032
R3076
R3072
R3069
C3020
C3022
X3001
R3067
R3068
C3028
R3099
R3100
C3033
C3023
C3018
C3036
C3038
C3039
R3055
R3051
R3056
R3052
C3008
R3012
R3018
R3008
R3013
D3003
D3001
C3004
R3009
L3002
L3001
C3002
R3017
C3009
C3005
R3007
D3002
D3004
C3003
R3050
R3049
R3048
R3047
R3046
R3045
R3044
C3011
C3015
C3014
C3013
C3012
R3057
R3058
R3062
R3063
R3064
R3065
R3066
C3026
R3070
R3071
R3073
R3074
R3077
R3086
R3088
R3090
R3091
R3092
R3093
R3095
R3053
C3016
C3017
C3025
C3034
C3041
C3040
L3003
L3004
R3014
R3011
R3015
R3016
R3019
R3010
EB4001
J3002
J3001
FB3001
IC3003
0.1
0.1
1M
0
0
0
10k
10k
10k
0.1
10k
10k
10k
10k
10k
10k
0.1
1k
10k
10k
10p
10p
24.576MHz
1k
1k
0.1
10k
10k
0.1
0.1
0.1
0.1
0.1
0.1
12k
680
12k
680
270p
10k
10k
56
56
1SS355
1SS355
0.1
56
1
56
270p
0.1
1M
1SS355
1SS355
1
100
100
100
100
100
100
1k
0.1
0.1
0.1
0.1
0.1
100
10k
100
100
100
100
100
0.1
100
100
100
10k
100
10k
10k
10k
10k
10k
10k
10k
0
0.1
0.1
0.1
0.1
0.1
220
10V
56
56
10k
56
10k
56
4P
4P
TSB43CA42PGF
A4
A5
B2
B3
B1
A1
A2
A3
B
CLK
D
SD
0
D
SD
1
D
SD2
D
SD3
D
SD
4
D
SD
5
MBCLK
LRCK
MBLA0
MBLA1
MBLA2
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
RD
HWR
WAIT
CS_MEMZ
CS_IOZ
D15
ARMINT
CLK
DIVVCO
REFSYT
VCOCLK
ICEM
95
8
MBLAA
AU
M
U
TE
SAS
YNC
FM
OD
E
FSS
EL1
R
XST
AR
T
SA
CH
SEL
FST
S0
FSTS1
SEL44K
FSSEL0
D
SDA
SELTYP1
SELTYP0
TA0P
TA0N
TB0P
TB0N
TB1N
TA1N
TB1P
TA1P
VSS
TESTMODE0
TESTMODE1
VDD
VCO_CLK
REF_SYT
DIV_VCO
PFD
MLPCM_BCLK
MLPCM_LRCK
MLPCM_D0
MLPCM_D1
MLPCM_D2
MLPCM_A
GPIO2
GPIO3
GPIO4
GPIO5
MSPCTL
VDD
VSS
CPS
AVDD
AGND
TPB0_N
TPB0_P
AGND
AVDD
TPA0_N
TPA0_P
TPBIAS0
AVDD
TPB1_N
TPB1_P
AGND
TPA1_N
TPA1_P
TPBIAS1
NC
NC
AVDD
NC
NC
NC
A
G
N
D
R
1
R
0
A
V
D
D
F
IL
T
E
R
0
F
IL
T
E
R
1
P
L
L
_
V
D
D
X
I
X
O
P
L
L
_
G
N
D
V
S
S
V
D
D
T
E
S
T
_
M
O
D
E
2
T
E
S
T
_
M
O
D
E
3
R
E
S
E
T
R
E
S
E
T
_
A
R
M
L
IN
K
_
O
N
H
P
S
L
O
W
_
P
W
R
_
R
D
Y
D
IS
A
B
L
E
_
IF
G
P
IO
0
G
P
IO
1
S
D
A
S
C
L
G
P
IO
6
G
P
IO
7
G
P
IO
8
G
P
IO
9
R
E
G
_
E
N
R
E
G
_
O
U
T
V
D
D
V
S
S
T
M
S
T
D
I
T
D
O
T
C
K
T
R
S
T
A
R
M
_
T
M
S
A
R
M
_
T
D
I
A
R
M
_
T
D
O
U
A
R
T
_
T
X
D
U
A
R
T
_
R
X
D
G
P
IO
1
0
T
M
R
WTCHDOG
V
S
S
V
D
D
H
S
D
I1
_
6
0
9
5
8
_
O
U
T
H
S
D
I1
_
6
0
9
5
8
_
IN
H
S
D
I1
_
A
U
D
IO
_
M
U
T
E
H
S
D
I1
_
A
U
D
IO
_
E
R
R
H
S
D
I1
_
A
M
C
L
K
_
O
U
T
H
S
D
I1
_
A
M
C
L
K
_
IN
H
S
D
I1
_
D
7
H
S
D
I1
_
D
6
H
S
D
I1
_
D
5
H
S
D
I1
_
D
4
H
S
D
I1
_
D
3
H
S
D
I1
_
D
2
H
S
D
I1
_
6
0
9
5
8
_
O
U
T
H
S
D
I1
_
6
0
9
5
8
_
IN
V
S
S
V
D
D
R
E
G
_
O
U
T
H
S
D
I1
_
D
1
H
S
D
I1
_
D
0
H
S
D
I1
_
E
N
H
S
D
I1
_
D
V
A
L
ID
H
S
D
I1
_
S
Y
N
C
H
S
D
I1
_
A
V
H
S
D
I1
_
C
L
K
H
S
D
I0
_
D
7
H
S
D
I0
_
D
6
H
S
D
I0
_
D
5
H
S
D
I0
_
D
4
H
S
D
I0
_
D
3
H
S
D
I0
_
D
2
V
S
S
V
D
D
H
S
D
I0
_
D
1
H
S
D
I0
_
D
0
H
S
D
I0
_
D
V
A
L
ID
H
S
D
I0
_
S
Y
N
C
H
S
D
I0
_
A
V
H
S
D
I0
_
E
N
H
S
D
I0
_
C
L
K
H
S
D
I0
_
A
M
C
L
K
_
IN
H
S
D
I0
_
6
0
9
5
8
_
IN
M
C
IF
_
M
O
D
E
2
M
C
IF
_
M
O
D
E
1
M
C
IF
_
M
O
D
E
2
M
C
IF
_
M
O
D
E
0
M
C
IF
_
IN
T
MCIF_CS_IO
MCIF_CS_MEM
MCIF_R_NW
MCIF_STRB
MCIF_WAIT
MCIF_ACK
MCIF_OE
MCIF_WE
MCIF_BUSCLK
MCIF_DATA0
MCIF_DATA1
VDD
VSS
MCIF_DATA2
MCIF_DATA3
MCIF_DATA4
MCIF_DATA5
MCIF_DATA6
MCIF_DATA7
MCIF_DATA8
MCIF_DATA9
MCIF_DATA10
MCIF_DATA11
MCIF_DATA12
MCIF_DATA13
REG_OUT
VSS
MCIF_DATA14
MCIF_DATA15
MCIF_ADDR1
MCIF_ADDR2
MCIF_ADDR3
MCIF_ADDR4
MCIF_ADDR5
MCIF_ADDR6
MCIF_ADDR7
MCIF_ADDR8
MCIF_ADDR9
MCIF_ADDR10
VDD
VSS
MCIF
ENDIAN
VDD
(CHASSIS)
(3/10)
I.LINK
S200
(AUDIO)
(AUDIO)
S200
I.LINK
(2)
(1)
I.LINK INTERFACE
(Page 92)
(Page 92)
(Page 95)
95
95
STR-DA7100ES
STR-DA7100ES
• See page 47 for IC Pin Function Description.
6-35. SCHEMATIC  DIAGRAM  – ILINK SECTION BOARD (4/10) –
R3122
R3127
R3129
R3132
R3133
R3135
R3137
R3140
R3147
FB3005
IC3016
C3091
C3090
C3087
C3086
C3085
C3084
IC3014
C3081
R3139
C3059
R3128
R3131
R3134
C3069
C3074
C3076
C3071
R3141
C3079
C3080
R3123
R3148
R3153
R3154
R3156
R3157
C3065
C3073
R3113
C3053
R3109
R3110
R3111
C3051
C3054
IC3005
C3047
IC3006
C3048
R3143
C3046
IC3004
R3107
R3106
FB3006
R3105
C3088
C3089
C3070
R3108
C3077
R3145
0
100
100
100
100
100
100
47
0
HY57V641620ETP
0.1
0.1
0.1
0.1
0.1
0.1
DB-ACP401
0.1
0
0.1
0
0
47
0.1
0.1
0.1
3.3
1.1k
220
10V
0.1
10k
100
100
100
100
100
0.1
0.1
10k
0.1
0
0
0
0.1
0.1
SN74AHC1G08DCKR
0.1
SN74AHC1G08DCKR
0.1
39k
0.1
TC74VHC00FT
100
100
100
47
10V
0.1
0.33
1k
0.1
220
C1
C2
C3
C4
C5
B1
B2
B3
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C22
C23
C24
C25
E1
CLK
CKE
A4
A5
A6
A7
A8
A9
A11
DQ9
DQ11
DQ13
DQ15
DQ8
DQ10
DQ12
DQ14
A
1
A
2
FMODE
SELTYP0
SELTYP1
SEL44K
FSSEL0
FSSEL1
RXSTART
SACHSEL
BCLK
DSD0
D
S
D
1
D
S
D
2
D
S
D
3
D
S
D
4
D
S
D
5
A
U
M
U
T
E
M
B
C
L
K
L
R
C
K
DQM
V
C
O
C
L
K
R
E
F
S
Y
T
D
IV
V
C
O
IC
E
M
9
5
8
M
B
L
A
A
M
B
L
A
2
M
B
L
A
1
M
B
L
A
0
SASYNC
FSTS1
FSTS0
D
S
D
A
A
0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
WE
CAS
RAS
A13
A12
A10
A0
A1
A2
A3
WE
CAS
RAS
DQM
CLK
CKE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
SEL512
CONT48
CLK48K
CLK48KI
CLK48KO
VSSO
VDDO
CONT44
CLK44K
CLK44KI
CLK44KO
SELOSC
XRESET
OUTPUTEN
FMODE
SELDTYPE0
SELDTYPE1
SEL44K
FSSEL0
FSSEL1
VSSO
VDDO
RXSTART
SACHSEL
FMUTE
FSTATE0
FSTATE1
FSTATE2
TDI
TDO
TMS
TCK
TRST
SANKIN
SAFRIN
SADOIN
V
S
S
C
O
V
D
D
C
O
S
A
D
1
IN
S
A
D
2
IN
S
A
D
3
IN
S
A
D
4
IN
S
A
D
5
IN
S
A
D
A
IN
A
M
C
K
IN
S
P
D
IFIN
S
D
M
U
T
E
IN
S
D
ER
R
IN
V
C
O
2
O
V
C
O
IN
V
C
O
E
N
VC
O
1
O
R
E
FS
Y
T
V
D
D
C
O
R
E
V
S
S
O
VS
S
PA
S
S
V
D
D
P
A
SS
L
P
O
U
T
L
P
IN
V
D
D
O
B
C
K
IN
L
R
CK
IN
S
D
A
1
IN
S
D
A
2
IN
S
D
A
3
IN
S
D
A
O
IN
V
S
S
O
V
D
D
O
S
D
A
0
SD
A
1
S
D
A2
V
S
S
CO
R
E
R
J
M
S
B
F
R
EFC
Y
C
L
E
S
A
P
C
M
M
D
P
L
L
M
D
T
E
S
T
M
D
1
T
E
S
T
M
D
0
S
A
F
R
O
S
A
D
5
S
A
D
4
V
D
D
C
O
R
E
V
S
S
C
O
R
E
S
A
D
3
S
A
D
2
S
AD
1
S
AD
0
S
A
D
A
O
S
A
M
C
K
O
S
A
PC
M
D
1
S
A
P
C
M
D
2
S
A
PC
M
D
3
SA
PC
M
L
R
C
K
S
AP
C
M
B
C
K
S
D
M
U
T
E
V
D
D
O
V
S
S
O
S
D
E
R
R
O
A
M
C
K
EN
A
M
C
K
O
B
C
K
O
L
R
C
KO
S
D
A
0
S
D
A
1
S
D
A
2
S
D
A
3
S
P
D
IF
O
VSSO
SDXWE
SDXCAS
SDARAS
SDDQM
SDCLK
SDCKE
SDD15
SDD14
SDD13
SDD12
SDD11
SDD10
SDD9
SDD8
VDDO
VSSO
SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0
SDA13
SDA12
SDA11
SDA10
SDA9
SDA8
SDA7
SDA6
SDA5
SDA4
SDA3
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
D10
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
(4/10)
V
D
D
O
SD-RAM
LEVEL SHIFT
LEVEL SHIFT
CLOCK SELECT
I.LINK DSP
(PD8112A)
(Page 92)
(Page 93)
(Page 93)
(Page 93)
(Page 93)
(Page 93)
(Page 94)
96
96
STR-DA7100ES
STR-DA7100ES
• See page 50 for IC Pin Function Description.
6-36. SCHEMATIC  DIAGRAM  – ILINK SECTION (5/10) –
Q3201
R3205
R3206
R3207
R3208
R3250
C3229
C3218
R3223
R3224
R3226
R3229
R3231
R3233
R3236
R3239
C3222
C3223
C3224
R3253
C3226
R3254
C3228
R3256
C3230
R3259
C3238
C3239
C3242
C3235
C3232
RB3207
C3249
C3248
C3247
C3246
C3245
C3244
R3263
C3250
RB3201
RB3202
RB3203
RB3204
RB3205
RB3206
C3217
C3220
C3221
R3252
C3225
C3227
C3243
R3261
C3237
C3234
C3240
R3260
R3248
R3246
R3244
R3241
R3238
R3235
R3228
C3231
X3201
R3255
L3203   10
µ
H
L3204   10
µ
H
L3202   10
µH
L3201   10
µH
C3215
C3213
C3212
C3211
C3210
C3209
C3208
C3207
C3206
C3214
C3204
C3205
R3214
R3213
R3212
Q3202
R3211
R3204
R3203
R3201
R3202
R3363
R3361
Q3209
Q3210
R3362
R3364
FB3203
FB3202
C3241
FB3201
C3236
C3233
C3251
CN3201
CN3202
IC3205
DTC144EUA-
47
47
47
47
47
10p
0.1
0
0
47
47
47
47
47
47
0.1
0.1
0.1
100
0.1
100
0.1
100
0.1
1.8k
0.01
0.1
0.1
10
16V
0.01
L3205
10
µH
47
0.1
0.1
0.1
0.1
0.1
220
4V
33
0.1
47
47
47
47
47
47
0.1
0.1
0.1
47
0.1
0.1
0.1
10k
0.1
0.1
0.1
1k
100
100
100
100
100
100
100
10p
28.322MHz
1M
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
100
6.3V
47
6.3V
47
47
1k
DTC144EUA-
1k
0
0
0
0
4.7k
4.7k
2SA1162
2SA1162
1k
1k
47
6.3V
0
47 6.3V
47 6.3V
220 4V
19P
19P
SII9031
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
H1
H2
H3
H4
H5
H6
H7
MUTEOUT
CXD3805_INT
CXD3805_RST
PROU_RST
VDAC_RST
ADGND
R0XC-
R0XC+
R0X0+
R0X1+
R0X2+
R0X2-
R0X0-
R0X1-
R1X1-
R1X2-
R1X0-
R1XC-
R1XC+
R1X0+
R1X1+
R1X2+
R1X2+
R1X1+
R1XC+
R1XC-
R1X0-
R1X1-
R1X2-
R1X0+
R0X0+
R0X1+
R0X2+
R0XC+
R0XC-
R0X0-
R0X1-
R0X2-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
S
P
D
IF
R
X
_
R
S
T
R
X
_
IN
T
C
S
C
L
C
S
D
A
HSYNC
VSYNC
DCK
DE
DSDA1
DSCL1
DSCL0
DSDA0
RX_HPD1
RX_HPD0
W
S
S
C
K
S
D
0
S
D
1
S
D
2
S
D
3
M
C
K
PROU_RST1
VDAC_RST
CXD3805_INT
CXD3805_RST
DATA2+
DATA2-
DATA1+
DATA2 SHIELD
DATA1 SHIELD
DATA1-
DATA0+
DATA0 SHIELD
DATA0-
CLOCK+
CLOCK SHIELD
CLOCK-
CEC
RESERVE(N.C.)
DCC/CEC GND
+5V POWER
HOT PLUG DET
SCL(5V)
SDA(5V)
DATA2+
DATA2-
DATA1+
DATA2 SHIELD
DATA1 SHIELD
DATA1-
DATA0+
DATA0 SHIELD
DATA0-
CLOCK+
CLOCK SHIELD
CLOCK-
CEC
RESERVE(N.C.)
DCC/CEC GND
+5V POWER
HOT PLUG DET
SCL(5V)
SDA(5V)
(5/10)
PVCC0
AVCC
R0XC-
R0XC+
AGND
AVCC
R0X0-
R0X0+
AGND
AVCC
R0X1-
ROX1+
AGND
AVCC
R0X2-
R0X2+
AGND
TMDSPGND
PVCC1
RSVD_A
AVCC
R1XC-
R1XC+
AGND
AVCC
R1X0-
R1X0+
AGND
AVCC
R1X1-
R1X1+
AGND
AVCC
R1X2-
R1X2+
AGND
D
G
N
D
D
V
CC
1
8
R
0P
W
R
5
V
R
1P
W
R
5
V
D
S
C
L
0
D
A
D
A
0
D
S
C
L
1
D
S
D
A
1
C
S
C
L
C
S
D
A
IO
V
C
C
IO
G
N
D
C
G
N
D
C
V
C
C
1
8
D
A
CD
V
C
C
1
8
D
AC
D
G
N
D
A
N
B
P
B
D
A
C
V
C
C
B
D
A
CG
N
D
B
A
N
G
Y
D
A
C
V
C
C
G
D
AC
G
N
D
G
A
N
R
P
R
D
A
C
VC
CR
D
A
C
G
N
D
R
C
O
M
P
R
S
E
T
V
R
EF
D
A
C
A
G
N
D
D
A
C
A
VC
C
D
AC
O
VC
C
IO
V
C
C
IO
G
N
D
V
S
Y
N
C
H
S
Y
N
C
D
E
Q0
Q1
Q2
Q3
Q4
CVCC18
CGND
Q5
Q6
IOGND
IOVCC
Q7
Q8
Q9
Q10
Q11
CVCC18
CGND
Q12
Q13
Q14
Q15
IOVCC
Q16
Q17
Q18
Q19
CGND
CVCC18
Q20
Q21
Q22
Q23
IOVCC
ODCK
IOGND
D
G
N
D
D
V
CC
18
IO
G
N
D
IO
VC
C
M
U
T
E
O
U
T
S
P
D
IF
CV
C
C
C
G
N
D
S
D
3
SD
2
S
D
1
S
D
0
W
S
S
C
K
M
C
K
IN
M
C
KO
U
T
IO
VC
C
IO
G
N
D
CG
N
D
C
V
CC
1
8
N
C
A
U
D
P
V
CC
1
8
A
U
D
PG
N
D
X
TA
L
O
U
T
X
TA
L
IN
X
T
A
LV
CC
R
E
G
V
C
C
N
C
R
S
VD
L
R
E
S
ET
S
C
D
T
IN
T
CV
CC
1
8
CG
N
D
C
L
K
48
B
IO
G
N
D
HDMI
ASSIGNABLE
IN 2
ASSIGNABLE
HDMI
IN 1
Q3202,3209
HOT PLUG
DETECT
DETECT
HOT PLUG
Q3201,3210
HDMI PANELLINK CINEMA RECEIVER
(Page 98)
(Page 93)
(Page 101)
(Page 98)
(Page 99)
(Page 100)
(Page 101)
(Page 97)
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