Sony STR-DA3700ES Service Manual ▷ View online
STR-DA3700ES
STR-DA3700ES
37
37
5-7. BLOCK DIAGRAM - HDMI Section (2/2) -
: AUDIO
: VIDEO
MAIN SYSTEM CONTROLLER
IC2501 (7/11)
HDMI RECEIVER
IC3511 (2/2)
HDMI TRANSMITTER
IC3513
HDMI_TX_RST1
49
CEC SEL
59
HDMI_TX_5VPWR1
48
HDMI_TX_INT1
57
CSCL
CSDA
CSDA, CSCL
Q0 – Q35
D0 – D35
ODCK 76
HSYNC 75
VSYNC 74
DE 73
106
105
100
100
SPDIF/DL2
SD0/DL0,
SD1/DR1,
SD2/DL1,
SD3/DR2
4
4
4
MCLK
SCK/DCLK
WS/DR0 99
IDCK
88
HSYNC
2
VSYNC
3
DE
1
SPDIF
DL0, DR1,
DL1, DR2
DL1, DR2
4
DL2
21
SD0 – SD3
MCLK
5
SCK
11
WS
10
DCLK
15
DR0
16
TX0+ 34
TX0– 33
TX0– 33
7
9
9
TX1+ 37
TX1– 36
TX1– 36
4
6
6
TX2+ 40
TX2– 39
TX2– 39
1
3
3
TXC+ 31
TXC– 30
TXC– 30
10
HPD
DATA0+
DATA0–
DATA0–
DATA1+
DATA1–
DATA1–
DATA2+
DATA2–
DATA2–
CLOCK+
CLOCK–
CLOCK–
SDA (5V)
SCL (5V)
SCL (5V)
HOT PLUG DET
CEC
51
19
12
16
15
15
13
RESERVE (NC)
14
DSDA 47
DSCL 46
INT 24
RESET# 25
CSDA 49
CSCL 48
CN3511
HDMI
OUT
ARC
HDMI_SPDIF
HDMI_LRCK
HDMI_BCK
SD0 – SD3
SD0 – SD3,
HDMI_BCK, HDMI_LRCK
R_SPDIF
HDMI_SPDIF
HDMI_SPDIF,
R_SPDIF
HDMI_SPDIF
5
4
XTALIN
XTALOUT4
X3501
27MHz
BUFFER
IC3524
+3.3V
REGULATOR
IC3860
RY3601
D-VIDEO +4V
HDMI +5V
(FOR TX)
(FOR TX)
96 – 88, 85 – 77,
70 – 62, 59 – 51
101 – 104
9 – 6
17 – 20
36
98 – 90, 86 – 77,
75 – 67, 63 – 56
36
16
CEC
HSYNC
SELECTOR
IC3204 – 3206
D[16] – D[23],
D[28] – D[35],
FLI_ODCK, FLI_HSYNC,
FLI_VSYNC, FLI_DE
D[28] – D[35],
FLI_ODCK, FLI_HSYNC,
FLI_VSYNC, FLI_DE
FLI_HSYNC
FLI_ODCK
D[16] – D[23], D[28] – D[35]
FLI_DE
FLI_VSYNC
FLI_ODCK
16
D-VIDEO +10V
+5V
REGULATOR
IC3516
44
43
43
137
136
136
143
142
142
141
140
140
139
138
138
42
41 R3PWR5V
R3X0+
R3X0–
R3X0–
R3X1+
R3X1–
R3X1–
R3X2+
R3X2–
R3X2–
R3XC+
R3XC–
R3XC–
HPD3
DSDA3
DSCL3
DSCL3
CN3506
7
9
9
4
6
6
1
3
3
10
DATA0+
DATA0–
DATA1+
DATA1–
DATA1–
DATA2+
DATA2–
DATA2–
CLOCK+
CLOCK–
CLOCK–
SDA (5V)
SCL (5V)
+5V POWER
HOT PLUG DET
18
CEC
13
12
16
15
15
19
HDMI
ASSIGNABLE
(INPUT ONLY)
IN 1 (GAME)
40
39
39
128
127
127
134
133
133
132
131
131
130
129
129
38
37 R2PWR5V
R2X0+
R2X0–
R2X0–
R2X1+
R2X1–
R2X1–
R2X2+
R2X2–
R2X2–
R2XC+
R2XC–
R2XC–
HPD2
DSDA2
DSCL2
DSCL2
CN3505
7
9
9
4
6
6
1
3
3
10
DATA0+
DATA0–
DATA1+
DATA1–
DATA1–
DATA2+
DATA2–
DATA2–
CLOCK+
CLOCK–
CLOCK–
SDA (5V)
SCL (5V)
+5V POWER
HOT PLUG DET
18
CEC
13
12
16
15
15
19
HDMI
ASSIGNABLE
(INPUT ONLY)
IN 2 (SAT/CATV)
CEC
45
HSYNC_TH
>024B
>025B
>049B
>029B
>001B
>013B
SIGNAL PATH
(Page 36)
(Page 42)
(Page 38)
(Page 36)
(Page 31)
(Page 32)
STR-DA3700ES
STR-DA3700ES
38
38
5-8. BLOCK DIAGRAM - VIDEO PROCESSING Section -
MAIN SYSTEM CONTROLLER
IC2501 (8/11)
VIDEO PROCESSOR
IC3601
FLI_BUSY
37
FSCLKP
D5
FSCLKN
C5
FLASH MEMORY
IC3615
SD-RAM
IC3618
A3P AF4
B1P AC2
A1P AB1
CVBS
PB OUT
PR OUT
PD0 – PD23
K23 – K26,J23, J24,
G23 –G26, F23 – F26,
E23, E24,
DCLK
P24
DHS
P25
DVS
R26
FLI_ODCK
FLI_HSYNC
FLI_VSYNC
FLI_VSYNC
DEN
P26
FLI_DE
C26
TCLK
B26
XTAL
X3602
19.6608MHz
F_D [0] – F_D [15]
F_A [1] – F_A [21]
FSDATA [16] – FSDATA [31]
FSADDR [0] – FSADDR [12]
FSADDR [0] – FSADDR [12]
FSCKE
C4
FSBKSEL0
C21
FSBKSEL1
C20
FSCS0
D21
FSRAS
C24
FSCAS
D24
FSWE
C23
FSDQM3
B22
FSDQM2
B17
FSDQS3
A22
45
46
44
26
27
24
23
22
21
20
47
16
46
44
26
27
24
23
22
21
20
47
16
A17
CLK
/CLK
CKE
BA0
BA1
BA1
CS
RAS
CAS
CAS
WE
LDM
UDM
LDQS
UDQS
CLK
/CLK
CKE
BA0
BA1
BA1
CS
RAS
CAS
CAS
WE
LDM
UDM
LDQS
UDQS
51
ROM_CS_N AD24
OCN_RE_N AC25
OCN_WE_N AC26
26
28
11
28
11
CE
OE
WE
OE
WE
12 RESET
FSDQS2
SD-RAM
IC3602
FSDATA [0] – FSDATA [15]
CLKP
CLKN
CKE
FSBKSEL0
FSBKSEL1
FSBKSEL1
FSCS0
RAS
CAS
CAS
WE
CLKP
CLKN
CKE
FSBKSEL0
FSBKSEL1
FSCS0
RAS
CAS
WE
FSDQM1
A11
FSDQM0
A6
FSDQS1
B11
45
46
44
26
27
24
23
22
21
20
47
16
46
44
26
27
24
23
22
21
20
47
16
B6
51
FSDQS0
FSDATA16 –
FSDATA31
FSDATA31
FSDATA0 –
FSDATA15
FSDATA15
DQ0 – DQ15
A0 – A12
DQ0 – DQ15
A0 – A20
F_A
[7]
DQ0 – DQ15
A0 – A12
FSADDR0 –
FSADDR12
FSADDR12
OCMDATA0 –
OCMDATA15
OCMADDR1 –
OCMADDR21
FLI_BOOT_SEL
35
MSTR1_SCL A3
UART_MAIN/FLI (TX)
OCM_UDI_1 B3
FLI_WAKE
36
LBADC_IN1 AF10
UART_FLI/MAIN (RX)
OCM_UDO_1 B2
FLI_RESET
38
144
145
145
RESET AD9
EEPROM
IC3621
DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS BUS
A2P AF1
B2P AE2
C2P AF2
CR
CB
CY
OCM_UDI_0 W25
ODM_UDO_0 W26
CSCL
CSDA
44
23 P_HSYNC
50 S_HSYNC
24 P_VSYNC
49 S_VSYNC
50 S_HSYNC
24 P_VSYNC
49 S_VSYNC
V
Y/G
SDA
21
SCLK
22
RESET
33
39
CVBS OUT1
CVBS OUT1,
CY OUT1,
CB OUT1,
CB OUT1,
CR OUT1
CY OUT1
CB/R 38
CB OUT1
CR/B 37
CR OUT1
FLI_HSYNC
FLI_VSYNC
FLI_DE
FLI_ODCK
DAC_CLK_SEL
VDAC_RESET
4 – 9, 12, 13,
16 – 18, 26 – 30
Y0 – Y7,
C0 – C7
25 P_BLANK
48 S_BLANK
48 S_BLANK
32 CLKIN_A
FREQUENCY
MULTIPLIER
IC3854
D/A CONVERTER
IC3850
2
8
5
IN
OUT2
FS1
VIDEO-DAC_RESET
V-DAC_CLOCK _SEL
DAC_CLK_SEL
VDAC_RESET
16
16
CSDA, CSCL
: VIDEO
MSTR0_SDA AA23
SDA
5
MSTR0_SCL AA24
SCL
6
D[16] – D[23],
D[28] – D[35]
D[28] – D[35]
D[16] – D[23],
D[28] – D[35],
FLI_ODCK, FLI_HSYNC,
FLI_VSYNC, FLI_DE
D[28] – D[35],
FLI_ODCK, FLI_HSYNC,
FLI_VSYNC, FLI_DE
D[16] - D[23],
D[28] - D[35]
D[28] - D[35]
C1P AC1
PY OUT
CVBS, CY
CB, CR
PY OUT,
PB OUT, PR OUT
46 47
FLASH_UPDATE_RX,
FLASH_UPDATE_TX
FLASH_UPDATE_TX
FLASH_UPDATE_RX
>088B
>035B
>037B
>085B
>032B
>049B
SIGNAL PATH
(Page 37)
(Page 41)
(Page 36)
(Page 41)
(Page 39)
(Page 42)
STR-DA3700ES
STR-DA3700ES
39
39
5-9. BLOCK DIAGRAM - NETWORK Section (1/2) -
CN2502
4
6
6
11
12
12
1
3
3
: AUDIO
: VIDEO
12
11
RXIM1
RXIP1
TXOM1
TXOP1
ETHERNET INTERFACE
IC2501
9
8
101 LED_LINK [1]
10
103 LED_FULL [1]
102 LED_SPEED [1]
87
88
RXD0_0
RXD0_1
RXD0_2
RXD0_3 85
RXD0_1
RXD0_2
RXD0_3 85
86
F25 ETRXD0
G27 ETRXD1
G28 ETRXD2
G25 ETRXD3
G28 ETRXD2
G25 ETRXD3
G23 ETTXD0
H23 ETTXD1
H23 ETTXD1
J23 ETTXD2
H26 ETTXD3
79
80
TXD0_0
TXD0_1
TXD0_2
TXD0_3 77
TXD0_1
TXD0_2
TXD0_3 77
78
71
70
MDIO0
MDC0
90
COL0
93
RESETB
RXDV0
MII0_RXCLK 89
84
MII0_TXCLK
TXEN0 76
81
J26 ETMDIO
J28 ETMDC
J28 ETMDC
E25 ETRXDV
G26 ETRXCLK
G24 ETTXCLK
H25 ETTXEN
G26 ETRXCLK
G24 ETTXCLK
H25 ETTXEN
J27 ETCOL
RESET SIGNAL
GENERATOR
IC2504
ETHER +3.3V
13
15
15
23
24
24
16
18
18
19
18
RXIM2
RXIP2
TXOM2
TXOP2
22
21
104 LED_LINK [2]
22
106 LED_FULL [2]
105 LED_SPEED [2]
28
30
30
35
36
36
25
27
27
30
29
RXIM3
RXIP3
TXOM3
TXOP3
27
26
107 LED_LINK [3]
34
109 LED_FULL [3]
108 LED_SPEED [3]
37
39
39
47
48
48
40
42
42
34
33
RXIM4
RXIP4
TXOM4
TXOP4
38
37
110 LED_LINK [4]
46
112 LED_FULL [4]
111 LED_SPEED [4]
4
3
2
1
: USB
AUDIO/VIDEO SIGNAL DECODER
IC101 (1/2)
USB_2P_DP0
AD2
USB_2P_DM0
AD1
CN1800
iPhone/iPod
3
2
2
VBUS
R-CH
1
9
PR OUT
12
PY OUT
10
PB OUT
VIDEO AMP
IC1003
PY IN
PB IN
PB IN
4
PR IN
5
3
CVBS IN
1
VDACG_OUT
VDACB_OUT B19
VDACR_OUT C18
A19
VDACX_OUT C19
14
CVBS OUT
16
AOUTR
1
AOUTL
D/A CONVERTER
IC901
LRCK
MCLK
MCLK
DACDAT
7
8
BCLK
9
PR OUT
PY OUT
PB OUT
PB OUT
CVBS OUT
D9
GPIO3
GPIO5
CH0_P B16
CH0_M A16
CH1_P B15
CH1_M A15
CH2_P B14
CH2_M A14
CLK_P B17
CLK_M A17
HTPLG D25
HDMISD D24
HDMISCK
DATA0+
DATA0+, DATA0–, DATA1+, DATA1–,
DATA2+, DATA2–, CLOCK+, CLOCK–,
SDA (5V), SCL (5V), HOT PLUG DETECT
DATA0–
DATA1+
DATA1–
DATA1–
DATA2+
DATA2–
DATA2–
CLOCK+
CLOCK–
CLOCK–
HOT PLUG DETECT
SDA (5V)
SCL (5V)
C25
AOSDATA0 C11
AOSDATA1 D11
AOSDATA2 D12
AOSDATA3 E10
AOSDATA1 D11
AOSDATA2 D12
AOSDATA3 E10
AOLRCK B12
AMUTE D10
AOSDATA0 – AOSDATA3,
AOBCK, AOLRCK, AMUTE
AOMCLK C12
AOSDATA4 F10
AOBCK
AOSDATA0
AOSDATA1
AOSDATA2
AOSDATA3
AOSDATA1
AOSDATA2
AOSDATA3
AOLRCK
AMUTE
AOBCK
A12
CVBS OUT, PY OUT,
PB OUT, PR OUT
PY OUT,
PB OUT, PR OUT
UART_MAIN/NET,
UART_NET/MAIN,
NET_RESET,
NET_ERROR,
NET_JIG_MODE1,
HUB_RESET,
NET_FAN_DETECT,
ACDC_STOP
ACDC_STOP
CPU_XRST
XMUTE
11
NET_FAN_DETECT
HUB_RESET
NET_JIG_MODE1
NET_ERROR
Q1103
NET_RESET
NET_L
+3.3VA
UART_NET/MAIN
UART_MAIN/NET
123
122
OSCI (X1)
X2
X2501
25MHz
AE6
E21
VDIN32
VDIN33 D20
RESET_ K23
RESET SIGNAL
GENERATOR
IC1103
10
TEMPARATURE
SENSOR
IC1108
THERMAL
DETECT
Q1104
>086B
>085B
>084B
>083B
>019B
>081B
>082B
SIGNAL PATH
R-ch is omitted due to same as L-ch.
(Page 36)
(Page 41)
(Page 38)
(Page 32)
(Page 34)
(Page 40)
(Page 42)
STR-DA3700ES
STR-DA3700ES
40
40
5-10. BLOCK DIAGRAM - NETWORK Section (2/2) -
UART_RX, UART_TX,
UART_SEL2
SD-RAM
IC106
RWE_
RA0 - RA13
RDQ0 - RDQ15
RCS_
AE13
AE15
AE15
L3
L2
L2
/WE
RBA0
AG14
M2
BA0
RBA1
AD19
N8
BA1
RBA2
AC15
M3
BA2
/CS
RCAS_
RRAS_
RRAS_
AD14
AC13
AC13
K3
J3
/CAS
/RAS
/RAS
RCKE
AG16
K9
CKE
RCLK0
AG24
J7
CK
RCLK0_
AH24
K7
/CK
RDQM1
RDQS1
RDQS1
AD21
AH21
AH21
D3
C7
C7
DMU
DQSU
RDQS1_
RDQM0
RDQM0
AG21
AE21
AE21
B7
E7
E7
/DQSU
DML
RODT
AC14
K1
ODT
RDQS0
AG20
F3
DQSL
RDQS0_
AH20
G3
/DQSL
T2
/RESET
A0 - A13
DQL0 - DQL7,
DQU0 - DQU7
SD-RAM
IC107
RDQ16 - RDQ31
RCLK1
AG13
RCLK1_
AH13
RDQM3
RDQS3
RDQS3
AD9
AH10
RDQS3_
RDQM2
RDQM2
AG10
AD10
AD10
RDQS2
AG9
RDQS2_
AH9
A0 - A13
DQL0 - DQL7,
DQU0 - DQU7
SD-RAM
IC206
A0 - A13
DQL0 - DQL7,
DQU0 - DQU7
SD-RAM
IC207
A0 - A13
DQL0 - DQL7,
DQU0 - DQU7
NAND FLASH
IC501
AUDIO/VIDEO SIGNAL DECODER
IC101 (2/2)
NFD0 - NFD7
D1A0 - D1A13
D0A0 - D0A13
D0A0 -
D0A13
D0A13
D1A0 - D1A13
NFWEN
AG4
18
WE
NFREN
AD4
8
RE
NFCEN
NFRBN
NFRBN
AH2
AE3
AE3
9
7
7
CE
RY/BY
NFALE
NFCLE
NFCLE
AF4
AG3
17
16
16
ALE
CLE
EEPROM
IC6601
VDIN31
C21
13
I2C_SDA
VDIN30
D21
12
I2C_SCL
4
RESET
19
WP
IO1 - IO8
X401
27MHz
NS_XTALO
NS_XTALI
B13
A13
CPU_XRST
T2
/RESET
RRESET
AC16
L3
L2
L2
/WE
M2
BA0
N8
BA1
M3
BA2
/CS
K3
J3
/CAS
/RAS
/RAS
K9
CKE
J7
CK
K7
/CK
D3
C7
C7
DMU
DQSU
B7
E7
E7
/DQSU
DML
K1
ODT
F3
DQSL
G3
/DQSL
L3
L2
L2
/WE
M2
BA0
N8
BA1
M3
BA2
/CS
K3
J3
/CAS
/RAS
/RAS
K9
CKE
J7
CK
K7
/CK
D3
C7
C7
DMU
DQSU
B7
E7
E7
/DQSU
DML
K1
ODT
F3
DQSL
G3
/DQSL
T2
/RESET
T2
/RESET
L3
L2
L2
/WE
M2
BA0
N8
BA1
M3
BA2
/CS
K3
J3
/CAS
/RAS
/RAS
K9
CKE
J7
CK
K7
/CK
D3
C7
C7
DMU
DQSU
B7
E7
E7
/DQSU
DML
K1
ODT
F3
DQSL
G3
/DQSL
RWE_B_
RA0_B - RA13_B
RDQ0_B - RDQ15_B
RCS_B_
AE28
AB25
AB25
RBA0_B
AB26
RBA1_B
T24
RBA2_B
W25
RCAS_B_
RRAS_B_
RRAS_B_
AC26
AD28
AD28
RCKE_B
V27
RCLK0_B
L27
RCLK0_B_
L28
RDQM1_B
RDQS1_B
RDQS1_B
R24
P28
P28
RDQS1_B_
RDQM0_B
RDQM0_B
P27
P25
P25
RODT_B
AD27
RDQS0_B
R27
RDQS0_B_
R28
RDQ16_B - RDQ31_B
RCLK1_B
AB27
RCLK1_B_
AB28
RDQM3_B
RDQS3_B
RDQS3_B
AE26
AF28
AF28
RDQS3_B_
RDQM2_B
RDQM2_B
AF27
AD26
AD26
RDQS2_B
AG27
RDQS2_B_
AG28
RRESET_B
Y26
F22
VDIN23
USB_PWREN
G9
GPIO2
NET_POW_RY
VDIN35/LIN G20
GPIO0 F9
UART_RX
UART_SEL2
VDIN34 F21
UART_TX
NET_ENDFLAG,
NET_MULTI_LED
NET_MULTI_LED
NET_ENDFLAG
GPIO6 AE5
GPIO1 E9
GPIO1 E9
>081B
>093B
>040B
>044B
>041B
(Page 39)
(Page 43)
(Page 42)
(Page 42)
(Page 42)
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