Sony STR-DA3300ES / STR-DG1100 Service Manual ▷ View online
121
STR-DA3300ES/DG1100
•
IC Pin Function Description
TUNER BOARD IC8003 F2602E-01-TR (XM RECEIVER)
Pin No.
Pin Name
I/O
Description
1
LSOPTXRX
-
Not used
2
VSS
-
Ground terminal
3
SCTXOUT
O
Serial data output to the system controller
4
VDD
-
Power supply terminal (+3.3V)
5
SCRXIN
I
Serial data input from the system controller
6
VSS
-
Ground terminal
7
COMMSEL
I
Command mode selection signal input terminal Not used
8
VDD
-
Power supply terminal (+3.3V)
9
IRQ
O
Interrupt request signal output terminal Not used
10
VSS
-
Ground terminal
11
RESET
I
Reset signal input from the system controller "L": reset
12
SLAVESL
I
Master/slave mode setting terminal "L": master mode, "H": slave mode
Fixed at "L" in this set
Fixed at "L" in this set
13
COMRXDIG
-
Not used
14
COMTXDIG
-
Not used
15
COMTXEN
-
Not used
16
VSS
-
Ground terminal
17
VDD
-
Power supply terminal (+3.3V)
18
COMRXP
I
XM receiver differential signal (positive) input terminal
19
COMRXM
I
XM receiver differential signal (negative) input terminal
20
VDD
-
Power supply terminal (+3.3V)
21
VSS
-
Ground terminal
22
COMTXM
O
XM transmitter differential signal (negative) output terminal
23
COMTXP
O
XM transmitter differential signal (positive) output terminal
24, 25
VSS
-
Ground terminal
26
OSCOUT
O
System clock output terminal (45.1584 MHz)
27
VDD
-
Power supply terminal (+3.3V)
28
OSCIN
I
System clock input terminal (45.1584 MHz)
29
VSS
-
Ground terminal
30
TEST
-
Not used
31
VSS
-
Ground terminal
32
HSDPDATA
-
Not used
33
VDD
-
Power supply terminal (+3.3V)
34
HSDPCLK
-
Not used
35
VSS
-
Ground terminal
36
HSDPEN
-
Not used
37
I2SDATA
O
I2S digital audio data output to the D/A converter and DSP
38
VSS
-
Ground terminal
39
I2SSCLK
O
I2S bit clock signal output to the D/A converter and DSP
40
VDD
-
Power supply terminal (+3.3V)
41
I2SLRCLK
O
I2S L/R sampling clock signal output to the D/A converter and DSP
42
VSS
-
Ground terminal
43
I2SOCLK
O
I2S over sample clock signal output to the D/A converter and DSP
44
VSS
-
Ground terminal
45
SAIICLK
-
Not used
46
VDD
-
Power supply terminal (+3.3V)
122
STR-DA3300ES/DG1100
Pin No.
Pin Name
I/O
Description
47
SAIIDATA
-
Not used
48
SAIIEN
-
Not used
123
STR-DA3300ES/DG1100
DSP BOARD IC2 ADSP21266SKSTZ-2C (DSP)
Pin No.
Pin Name
I/O
Description
1
VDDINT
-
Power supply terminal (+1.2V)
2, 3
CLKCFG0,
CLKCFG1
I
Clock frequency setting terminal
4, 5
BOOTCFG0,
BOOTCFG1
I
Boot mode setting terminal for DSP
6
GND
-
Ground terminal
7
VDDEXT
-
Power supply terminal (+3.3V)
8
GND
-
Ground terminal
9
VDDINT
-
Power supply terminal (+1.2V)
10
GND
-
Ground terminal
11
VDDINT
-
Power supply terminal (+1.2V)
12
GND
-
Ground terminal
13
VDDINT
-
Power supply terminal (+1.2V)
14
GND
-
Ground terminal
15
INT_REQ
O
Interrupt request signal output to the system controller
16
DIR_ERR
I
PLL lock error signal and data error flag input from the digital audio interface receiver
17
AD7
I/O
Two-way data bus with S-RAM and address signal output to the S-RAM
18
GND
-
Ground terminal
19
VDDINT
-
Power supply terminal (+1.2V)
20
GND
-
Ground terminal
21
VDDEXT
-
Power supply terminal (+3.3V)
22
GND
-
Ground terminal
23
VDDINT
-
Power supply terminal (+1.2V)
24 to 26
AD6 to AD4
I/O
Two-way data bus with S-RAM and address signal output to the S-RAM
27
VDDINT
-
Power supply terminal (+1.2V)
28
GND
-
Ground terminal
29, 30
AD3, AD2
I/O
Two-way data bus with S-RAM and address signal output to the S-RAM
31
VDDEXT
-
Power supply terminal (+3.3V)
32
GND
-
Ground terminal
33, 34
AD1, AD0
I/O
Two-way data bus with S-RAM and address signal output to the S-RAM
35
XWR
O
Data write enable signal output to the S-RAM
36, 37
VDDINT
-
Power supply terminal (+1.2V)
38
GND
-
Ground terminal
39
XRD
O
Data read enable signal output to the S-RAM
40
ALE
O
Address latch enable signal output terminal
41 to 43
AD15 to AD13
I/O
Two-way data bus with S-RAM and address signal output to the S-RAM
44
GND
-
Ground terminal
45
VDDEXT
-
Power supply terminal (+3.3V)
46
AD12
I/O
Two-way data bus with S-RAM and address signal output to the S-RAM
47
VDDINT
-
Power supply terminal (+1.2V)
48
GND
-
Ground terminal
49 to 52
AD11 to AD8
I/O
Two-way data bus with S-RAM and address signal output to the S-RAM
53
A16
O
Address signal output to the S-RAM
54
VDDINT
-
Power supply terminal (+1.2V)
55
GND
-
Ground terminal
56, 57
A17, A18
O
Address signal output to the S-RAM
124
STR-DA3300ES/DG1100
Pin No.
Pin Name
I/O
Description
58
GND
-
Ground terminal
59
VDDEXT
-
Power supply terminal (+3.3V)
60
VDDINT
-
Power supply terminal (+1.2V)
61
GND
-
Ground terminal
62
PF_CE
I/O
Chip enable signal input/output terminal Not used
63
SPI_MAS
O
Master/slave selection signal output to the system controller "L": DSP is master
64
DPSOA
O
PCM audio signal (front L/R) output to the D/A converter
65
DPSOB
O
PCM audio signal (surround L/R) output to the D/A converter
66
VDDINT
-
Power supply terminal (+1.2V)
67
GND
-
Ground terminal
68
VDDINT
-
Power supply terminal (+1.2V)
69
GND
-
Ground terminal
70
DPSOC
O
PCM audio signal (center, sub woofer) output to the D/A converter
71
DPSOD
O
PCM audio signal (surround back L/R) output to the D/A converter
72
VDDINT
-
Power supply terminal (+1.2V)
73
VDDEXT
-
Power supply terminal (+3.3V)
74
GND
-
Ground terminal
75
VDDINT
-
Power supply terminal (+1.2V)
76
GND
-
Ground terminal
77
DPSOE
O
PCM audio signal output terminal Not used
78
DPSIA
I
PCM audio signal (digital input) input from the digital audio interface receiver
79
DPSIB
I
PCM audio signal (front L/R) input from the A/D converter, HDMI receiver or XM receiver
80
DPSIC
I
PCM audio signal (surround L/R) input from the HDMI receiver
81
DPSID
I
PCM audio signal (center, sub woofer) input from the HDMI receiver
82
DPSIE
I
PCM audio signal (surround back L/R) input from the HDMI receiver
83
VDDINT
-
Power supply terminal (+1.2V)
84, 85
GND
-
Ground terminal
86
DPDVLRCK
O
L/R sampling clock signal output for PCM audio output to the D/A converter
87
DPDVBCK
O
Bit clock signal output for PCM audio output to the D/A converter
88
DPLRCK
I
L/R sampling clock signal input for PCM audio input from the digital audio interface receiver,
HDMI receiver or XM receiver
HDMI receiver or XM receiver
89
DPBCK
I
Bit clock signal input for PCM audio input from the digital audio interface receiver, HDMI
receiver or XM receiver
receiver or XM receiver
90
VDDINT
-
Power supply terminal (+1.2V)
91, 92
GND
-
Ground terminal
93
VDDEXT
-
Power supply terminal (+3.3V)
94
DPFSCK
I
Master clock signal input from the digital audio interface receiver, HDMI receiver or XM receiver
95
GND
-
Ground terminal
96
VDDINT
-
Power supply terminal (+1.2V)
97
XNONAUDIO
I
PCM audio data input from the digital audio interface receiver
98
XSF_CE
O
Chip enable signal output to the serial flash
99
VDDINT
-
Power supply terminal (+1.2V)
100
GND
-
Ground terminal
101
VDDINT
-
Power supply terminal (+1.2V)
102
GND
-
Ground terminal
103
VDDINT
-
Power supply terminal (+1.2V)
104
GND
-
Ground terminal
105
VDDINT
-
Power supply terminal (+1.2V)
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