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25

•

Pin No.

Pin Name

I/O

Description

1

DISEL

I

Selection terminal of data input terminal    Fixed at “L” in this set

2

DOUT

O

Digital data output to the optical transceiver (IC609)

3

DIN0

I

Digital data input from the optical receiver (IC952) (for CDP-S3)

4

DIN1

I

Digital data input from the optical receiver (IC951) (for external input)

5

DIN2

I

Digital data input terminal    Not used (fixed at “L”)

6

DGND

—

Ground terminal (digital system)

7

DVDD

—

Power supply terminal (+3.3V) (digital system)

8

R

I

VCO gain control input terminal

9

VIN

I

VCO free run frequency setting input terminal

10

LPF

O

PLL loop filter setting output terminal

11

AVDD

—

Power supply terminal (+3.3V) (analog system)

12

AGND

—

Ground terminal (analog system)

13

CKOUT

O

Audio clock signal output to the CXD9617R (IC601)

14

BCK

O

Bit clock signal (2.8224 MHz) output to the CXD9617R (IC601)

15

LRCK

O

L/R sampling clock signal (44.1 kHz) output to the CXD9617R (IC601)

16

DATAO

O

Audio serial data output to the CXD9617R (IC601)

17

XSTATE

O

Source clock switching monitor output to the system controller (IC501)

18

DGND

—

Ground terminal (digital system)

19

DVDD

—

Power supply terminal (+3.3V) (digital system)

20

XMCK

O

Oscillation clock signal output to the CXD9617R (IC601)

21

XOUT

O

System clock output terminal (13.5 MHz)

22

XIN

I

System clock input terminal (13.5 MHz)

23

EMPHA

O

Emphasis information of channel status output terminal    Not used (open)

24

AUDIO

O

Bit 1 output terminal of channel status to the CXD9617R (IC601)

25

CSFLAG

O

Top 40 bit renovation flag output terminal of channel status    Not used (open)

26 to 28

F0 to F2

O

Input frequency calculation result output terminal    Not used (open)

29

VF

O

Validity flag output terminal    Not used (open)

30

DVDD

—

Power supply terminal (+3.3V) (digital system)

31

DGND

—

Ground terminal (digital system)

32

ERR9P

O

Nine times continuance data transmission error flag output terminal    Not used (open)

33

BPSYNC

O

Non-PCM burst and preamble sync signal output terminal    Not used (open)

34

ERROR

O

PLL lock error and data error flag output to the system controller (IC501)

35

DO

O

Read data output to the system controller (IC501)

36

DI

I

Write data input from the system controller (IC501)

37

CE

I

Chip enable signal input from the system controller (IC501)

38

CL

I

Clock signal input from the system controller (IC501)

39

XSEL

I

Selection input terminal of vibrator frequency terminal    Fixed at “H” in this set

40

MODE0

I

Mode setting input terminal    Fixed at “H” in this set

41

MODE1

I

Mode setting input terminal    Fixed at “H” in this set

42

DGND

—

Ground terminal (digital system)

43

DVDD

—

Power supply terminal (+3.3V) (digital system)

44

DOSEL0

I

Output data format selection signal input terminal    Fixed at “L” in this set

45

DOSEL1

I

Output data format selection signal input terminal    Fixed at “L” in this set

46

CKSEL0

I

Output clock selection signal input terminal    Fixed at “L” in this set

47

CKSEL1

I

Output clock selection signal input terminal    Fixed at “L” in this set

48

XMODE

I

System reset signal input from the M61512FP (IC607)

26

•

Pin No.

Pin Name

I/O

Description

1

SDOS

I

Audio serial data source selection signal input terminal
“L”: internal ADC output, “H”: DAUX input (fixed at “L” in this set)                                               

2

I2C

I

Serial control mode selection signal input terminal    “L”: 3-wire serial, “H”: I2C bus                      

3

SMUTE

I

Soft muting on/off signal input from the system controller (IC501)    “L”: muting on

4

BICK

I

Bit clock signal (2.8224 MHz) input from the CXD9617R (IC601)

5

LRCK

I

L/R sampling clock (44.1 kHz) signal input from the CXD9617R (IC601)

6 to 8

SDTI1 to SDIT3

I

Audio serial data input from the CXD9617R (IC601)

9

SDTO

O

Audio serial data output to the CXD9617R (IC601)

10

DAUX

I

Audio serial data input terminal    Not used (fixed at “L”)

11

DFS

I

Double speed sampling mode signal input terminal
“L”: normal speed, “H”: double speed (fixed at “L” in this set)

12

DEM1

I

De-emphasis signal input terminal    Fixed at “L” in this set

13

DEM0

I

De-emphasis signal input terminal    Fixed at “H” in this set

14

TVDD

—

Power supply terminal (+5V) (for output buffer )

15

DVDD

—

Power supply terminal (+5V) (digital system)

16

DVSS

—

Ground terminal (digital system)

17

PDN

I

Power down and reset signal input from the M61512FP (IC607)    “L”: power down and reset

18 to 20

ICKS2 to ICKS0

I

Input clock signal selection terminal    Fixed at “L” in this set

21, 22

CAD1, CAD0

I

Chip address signal input terminal    Not used (fixed at “L”)

23

LOUT3

O

Analog signal output for center to the M61512FP (IC607)

24

ROUT3

O

Analog signal output for sub woofer to the M61512FP (IC607)

25

LOUT2

O

Analog signal output for surround L-ch to the M61512FP (IC607)

26

ROUT2

O

Analog signal output for surround R-ch to the M61512FP (IC607)

27

LOUT1

O

Analog signal output for front L-ch to the M61512FP (IC607)

28

ROUT1

O

Analog signal output for front R-ch to the M61512FP (IC607)

29

LIN–

I

L-ch analog signal negative input from the M61512FP (IC607)

30

LIN+

I

L-ch analog signal positive input from the M61512FP (IC607)

31

RIN–

I

R-ch analog signal negative input from the M61512FP (IC607)

32

RIN+

I

R-ch analog signal positive input from the M61512FP (IC607)

33

DZF2

O

Zero input detection terminal     Not used (open)

34

VCOM

O

Common voltage output terminal                                                                                                         
Large external capacitor is used to reduce power supply noise

35

VREFH

I

Reference voltage (+5V) input terminal

36

AVDD

—

Power supply terminal (+5V) (analog system)

37

AVSS

—

Ground terminal (analog system)

38

DZF1

O

Zero input detection terminal     Not used (open)

39

MCLK

I

Master clock signal input from the CXD9617R (IC601)

40

P/S

I

Parallel/serial selection signal input terminal
“L”: serial control mode, “H”: parallel control mode (fixed at “H” in this set)

41

DIF0

I

Audio data interface format terminal    Fixed at “L” in this set

42

DIF1

I

Audio data interface format terminal    Fixed at “H” in this set

43, 44

LOOP0, LOOP1

I

Loop back mode setting terminal    Fixed at “L” in this set

27

•

Pin No.

Pin Name

I/O

Description

1 to 6

G6 to G1

O

Grid drive signal output to the fluorescent indicator tube (FL601)

7 to 10

A1 to A4

O

Segment drive signal output to the fluorescent indicator tube (FL601)

11

VSS FOR IO

—

Ground terminal (for I/O)

12 to 22

A5 to A15

O

Segment drive signal output to the fluorescent indicator tube (FL601)

23

VDD FOR VFT

—

Power supply terminal (+3.3V) (for VFT)

24 to 41

A16 to A33

O

Segment drive signal output to the fluorescent indicator tube (FL601)

42

VSS FOR IO

—

Ground terminal (for I/O)

43 to 47

A34 toA38

O

Segment drive signal output to the fluorescent indicator tube (FL601)

48

VKK FOR VFT

—

Power supply terminal (–28V) (for VFT)

49

MODE0

—

Chip mode selection terminal     Not used (fixed at  “H”)

50

MODE1

—

Chip mode selection terminal     Not used (fixed at  “H”)

51

MODE2

—

Chip mode selection terminal     Not used (fixed at  “L”)

52

JOG2B

I

Jog dial pulse input from the rotary encoder (for sound) in the TA-S7AV (B phase input)

53

JOG2A

I

Jog dial pulse input from the rotary encoder (for sound) in the TA-S7AV (A phase input)

54

JOG1B

I

Jog dial pulse input from the rotary encoder (for function) in the TA-S7AV (B phase input)

55

JOG1A

I

Jog dial pulse input from the rotary encoder (for function) in the TA-S7AV (A phase input)

56

VOLA

I

Jog dial pulse input from the rotary encoder (for volume) in the TA-S7AV (A phase input)

57

VOLB

I

Jog dial pulse input from the rotary encoder (for volume) in the TA-S7AV (B phase input)

58, 59

—

—

Not used (open)

60

I2C DATA

I/O

Communication data bus with the system controller (IC501) and CDP-S3

61

I2C CLK

I/O

Communication data reading clock signal input or transfer clock signal output with the system 
controller (IC501) and CDP-S3

62

AVCC FOR 

ANALOG

—

Power supply terminal (+3.3V) (for analog)

63

AVSS FOR 

ANALOG

—

Ground terminal (for analog)

64

KEY0

I

Key input terminal (A/D input)    CLOCK/TIMER, TIMER SELECT, TUNER/BAND, TUNING 
+/–, ENTER,  PRESET +/–, TUNER MEMORY, STEREO/MONO, PTY (S602 to S612) keys 
input    PTY (S612) key: Used for the AEP and UK models only

65

KEY1

I

Key input terminal for TA-S7AV (A/D input)

66 to 76

—

—

Not used (open)

77

RESET

I

Reset signal input from the system controller (IC501)    “L”: reset

78 to 80

—

—

Not used (open)

81

VSS FOR CPU

—

Ground terminal (for CPU)

82

XIN

I

System clock input terminal (4 MHz)

83

XOUT

O

System clock output terminal (4 MHz)

84

VCC FOR CPU

—

Power supply terminal (+3.3V)

85 to 91

—

—

Not used (open)

92 to 94

G12

O

Grid drive signal output to the fluorescent indicator tube (FL601)

95 to 98

G11 to G8

O

Grid drive signal output to the fluorescent indicator tube (FL601)

99, 100

G7

O

Grid drive signal output to the fluorescent indicator tube (FL601)

28

• Items marked “*” are not stocked since they

are seldom required for routine service. Some
delay should be anticipated when ordering
these items.

• The mechanical parts with no reference num-

ber in the exploded views are not supplied.

NOTE:

• -XX and -X mean standardized parts, so they

may have some difference from the original
one.

• Color Indication of Appearance Parts

Example:
KNOB, BALANCE (WHITE) . . . (RED)

↑

↑

Parts Color Cabinet's Color

• Abbreviation

AUS : Australian model
KR

: Korean model

MX : Mexican model

Ref. No.

Part No.

Description

Remark

Ref. No.

Part No.

Description

Remark

1

X-4953-451-1 PANEL ASSY (ST), FRONT (AEP, UK)

1

X-4953-452-1 PANEL ASSY (ST), FRONT (KR, MX, AUS)

2

1-773-114-11 WIRE (FLAT TYPE) (19 CORE)

3

4-232-351-01 FILTER (FL)

4

1-680-697-11 SIRCS BOARD

5

4-951-620-01 SCREW (2.6X8), +BVTP

6

A-4476-267-A PANEL BOARD, COMPLETE (AEP, UK)

6

A-4476-269-A PANEL BOARD, COMPLETE (KR, MX, AUS)

7

3-363-099-21 SCREW (CASE 3 TP2)

8

4-233-134-31 COVER

#1

7-685-646-79 SCREW +BVTP 3X8 TYPE2 N-S

#2

7-685-871-01 SCREW +BVTT 3X6 (S)