Sony ST-S5 Service Manual ▷ View online
21
ST-S5
5-10.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC501 M30622MGA-A39FP (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
AMP-DATA
O
Serial data output to the M61512FP (IC607)
2
AMP-CLK
O
Serial data transfer clock signal output to the M61512FP (IC607)
3
AMP-LAT
O
Serial data latch pulse signal output to the M61512FP (IC607)
4
SIRCS
I
Remote control signal input from the remote control receiver (IC101)
5
DIG-TX
O
Serial data output to the CXD9617R (IC601), digital audio interface receiver (IC604) and digital
filter (IC606)
filter (IC606)
6
DSP-RX
I
Serial data input from the digital audio interface receiver (IC604)
7
DIG-CLK
O
Serial data transfer clock signal output to the CXD9617R (IC601), digital audio interface receiver
(IC604) and digital filter (IC606)
(IC604) and digital filter (IC606)
8
GND
—
Ground terminal
9
CNVSS
—
Not used
10
XCIN
I
Sub system clock input terminal (32.768 kHz)
11
XCOUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal generator (IC551) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13
XOUT
O
Main system clock output terminal (16 MHz)
14
VSS
—
Ground terminal
15
XIN
I
Main system clock input terminal (16 MHz)
16
VCC
—
Power supply terminal (+5V)
17
NMI
I
Non-maskable interrupt input terminal Fixed at “H” in this set
18
RDS-INT
I
Serial data transfer clock signal from the RDS decoder on the FM/AM tuner unit
19
—
—
Not used (open)
20
RDS-DATA
I
Serial data input from the RDS decoder on the FM/AM tuner unit
21
ST-MUTE
O
Tuner muting on/off control signal output to the FM/AM tuner unit “L”: muting on
22
ST-CE
O
Chip enable signal output to the FM/AM tuner unit
23
ST-DOUT
O
Serial data output to the FM/AM tuner unit
24
—
—
Not used (open)
25
ST-DIN
I
Serial data input from the FM/AM tuner unit
26
—
—
Not used (open)
27
ST-CLK
O
Serial data transfer clock signal output to the FM/AM tuner unit
28
—
—
Not used (open)
29
IIC CLK
I/O
Communication data reading clock signal input or transfer clock signal output with the display
controller (IC601) and CDP-S3
controller (IC601) and CDP-S3
30
IIC DATA
I/O
Communication data bus with the display controller (IC601) and CDP-S3
31 to 34
NO-USE
—
Not used
35 to 40
—
—
Not used (open)
41
M-RESET
O
Reset signal output to the display controller (IC601) “L”: reset
42 to 50
—
—
Not used (open)
51
NO-USE
—
Not used
52 to 57
—
—
Not used (open)
58
EXP-IN DATA
I
Serial data input from the I/O expander in the TA-S7AV
59
EXP-OUT DATA
O
Serial data output to the I/O expander in the TA-S7AV
60
EXP-LAT
O
Serial data latch pulse signal output to the I/O expander in the TA-S7AV
61
EXP-CLK
O
Serial data transfer clock signal output to the I/O expander in the TA-S7AV
62
VCC
—
Power supply terminal (+5V)
63
SOFT-TEST
I
Soft test output terminal Not used (open)
22
ST-S5
Pin No.
Pin Name
I/O
Description
64
VSS
—
Ground terminal
65 to 70
—
—
Not used (open)
71
LINE-MUTE
O
Audio line muting on/off control signal output to the audio line circuit “L”: muting on
72
—
—
Not used (open)
73
DISPLAY KEY
I
DISPLAY switch (S601) input terminal
74
POWER KEY
I
Power on/off switch in the TA-S7AV input terminal
75
DIR-UNLOCK
I
PLL lock error and data error flag input from the digital audio interface receiver (IC604)
76
DIR-CS
O
Chip enable signal output to the digital audio interface receiver (IC604)
77
DIR-XSTATE
I
Source clock switching monitor input from the digital audio interface receiver (IC604)
78
DIR-RX
I
Read data input from the digital audio interface receiver (IC604)
79
CODEC-SMUTE
O
Soft muting on/off control signal output to the A/D, D/A converter (IC605) “L”: muting on
80
DSP-ACK
I
Acknowledge signal input from the CXD9617R (IC601)
81
DSP-CS
O
Chip select signal output to the CXD9617R (IC601)
82
DSP-DECODE
O
Decode signal input from the CXD9617R (IC601)
83 to 86
—
—
Not used (open)
87
STEREO
I
FM stereo detection signal input from the FM/AM tuner unit “L”: stereo
88
TUNED
I
Tuning detection signal input from the FM/AM tuner unit “L”: tuned
89 to 91
—
—
Not used (open)
92
MODEL-IN
I
Model setting terminal
93
SPEC-IN
I
Specification setting terminal
94
—
—
Not used (open)
95
V-MUTE
O
Video muting on/off control signal output terminal “L”: muting on Not used (open)
96
AVSS
—
Ground terminal
97
—
—
Not used (open)
98
VREF
I
Reference voltage (+5V) input terminal
99
AVCC
—
Power supply terminal (+5V)
100
AC-CUT
I
AC cut on/off detection signal input from the reset signal generator (IC551)
“L”: AC cut on, “H”: AC cut off or checked
“L”: AC cut on, “H”: AC cut off or checked
23
ST-S5
•
DSP BOARD IC601 CXD9617R (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
XRST
I
Reset signal input from the M61512FP (IC607) “L”: reset
3
EXTIN
I
Master clock signal input terminal Not used (fixed at “L”)
4
FS2
I
Sampling frequency selection signal input terminal Not used (fixed at “L”)
5
VDDI
—
Power supply terminal (+2.6V)
6
FS1
I
Sampling frequency selection signal input terminal Not used (fixed at “L”)
7
PLOCK
O
Internal PLL lock signal output terminal Not used (open)
8
VSS
—
Ground terminal
9
MCLK1
I
Oscillation clock signal input from the digital audio interface receiver (IC604)
10
VDDI
—
Power supply terminal (+2.6V)
11
VSS
—
Ground terminal
12
MCLK2
O
Oscillation clock signal output terminal Not used (open)
13
MS
I
Master/slave selection signal input terminal “L”: slave, “H”: master (fixed at “L” in this set)
14
SCKOUT
O
Internal system clock signal output to the digital filter (IC606)
15
LRCKI1
I
L/R sampling clock signal (44.1 kHz) input terminal Not used (open)
16
VDDE
—
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input terminal Not used (open)
18
SDI1
I
Audio serial data input from the D/A, A/D converter (IC605)
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the D/A, A/D converter (IC605) and digital filter
(IC606)
(IC606)
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the D/A, A/D converter (IC605) and digital filter (IC606)
21
VSS
—
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver (IC604)
23 to 25
SDO1 to SDO3
O
Audio serial data output to the A/D, D/A converter (IC604)
26
SDO4
O
Audio serial data output to the digital filter (IC606)
27
SPDIF
O
S/PIDF signal output terminal Not used (open)
28
LRCKI2
I
L/R sampling clock signal (44.1 kHz) input from the digital audio interface receiver (IC604)
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the digital audio interface receiver (IC604)
30
SDI2
I
Audio serial data input from the digital audio interface receiver (IC604)
31
VSS
—
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller (IC501)
33
HDIN
I
Write data input from the system controller (IC501)
34
HCLK
I
Clock signal input from the system controller (IC501)
35
HDOUT
O
Read data output to the system controller (IC501)
36
HCS
I
Chip select signal input from the system controller (IC501)
37
SDCLK
O
Clock signal output terminal Not used (open)
38
CLKEN
O
Clock enable signal output terminal Not used (open)
39
RAS
O
Row address strobe signal input terminal Not used (open)
40
VDDI
—
Power supply terminal (+2.6V)
41
VSS
—
Ground terminal
42
CAS
O
Column address strobe signal output terminal Not used (open)
43
DQM
O
Output terminal of data input/output mask Not used (open)
44
CS0
O
Chip select signal output to the S-RAM (IC602)
45
WE0
O
Write enable signal output to the S-RAM (IC602)
46
VDDE
—
Power supply terminal (+3.3V)
47
WMD1
I
S-RAM wait mode setting terminal Fixed at “H” in this set
24
ST-S5
Pin No.
Pin Name
I/O
Description
48
VSS
—
Ground terminal
49
WMD0
I
S-RAM wait mode setting terminal Fixed at “L” in this set
50
PAGE2
O
Page selection signal output terminal Not used (open)
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
Page selection signal output terminal Not used (open)
54
BOOT
I
Boot mode control signal output terminal Not used (fixed at “L”)
55
BTACT
I
Boot mode state display signal output terminal Not used (open)
56
BST
I
Boot trap signal input from the M61512FP (IC607)
57
MOD1
I
PLL input frequency select terminal “L”: 384fs, “H”: 256fs (fixed at “H” in this set)
58
MOD0
I
Mode setting terminal “L”: single chip mode, “H”: use prohibition (fixed at “L” in this set)
59
EXLOCK
I
PLL lock error and data error flag input from the digital audio interface receiver (IC604)
60
VDDI
—
Power supply terminal (+2.6V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used (open)
64 to 66
A15 to A13
O
Address signal output to the S-RAM (IC602)
67
GP10
O
L/R sampling clock signal (44.1 kHz) output to the D/A, A/D converter (IC605) and digital filter
(IC606)
(IC606)
68
DECODE
O
Decode signal output to the system controller (IC501)
69
AUDIO
I
Bit 1 input terminal of channel status from the digital audio interface receiver (IC604)
70
VDDI
—
Power supply terminal (+2.6V)
71
VSS
—
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM (IC602)
76
VDDE
—
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM (IC602)
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM (IC602)
86
TDO
O
Simple emulation data output terminal Not used (open)
87
TMS
I
Simple emulation data input start/end detection signal input terminal Not used (open)
88
XTRST
I
Simple emulation asychronous break input terminal Not used (open)
89
TCK
I
Simple emulation clock signal input terminal Not used (open)
90
TDI
I
Simple emulation data input terminal Not used (open)
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM (IC602)
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM (IC602)
100
VDDI
—
Power supply terminal (+2.6V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM (IC602)
106
VDDE
—
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM (IC602)
109, 110
A2, A1
O
Address signal output to the S-RAM (IC602)
111
VSS
—
Ground terminal
112
A0
O
Address signal output to the S-RAM (IC602)
113
PM
I
PLL reset signal input from the M61512FP (IC607) “L”: reset
114, 115
SDI3, SDI4
I
Audio serial data input terminal Not used (fixed at “L”)
116
SYNC
I
Synchronous/asychronous selection signal input terminal
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
117 to 119
VSS
—
Ground terminal
120
VDDI
—
Power supply terminal (+2.6V)
Click on the first or last page to see other ST-S5 service manuals if exist.