Sony SS-US501 / SW-US501 / UZ-US501 Service Manual ▷ View online
29
SS-US501/SW-US501/UZ-US501
Pin No.
Pin Name
I/O
Description
56
LCD-CS
O
Chip select signal output to the LCD driver “L” active
57
NC
—
Not used
58
BVDD
—
Power supply terminal (+3.3V) (for bus interface)
59
BVSS
—
Ground terminal (for bus interface)
60, 61
NC
—
Not used
62
READY-H
O
Power on/off control signal output terminal with APC “H”: power on
63, 64
NC
—
Not used
65
HP MUTE
O
Headphone muting on/off control signal output terminal “H”: muting on
66
HP S/W
I
Headphone detection signal input terminal “H”: headphone in
67
APC LED
O
LED drive signal output of APC indicator “H”: LED on
68
VOL-STB
O
Serial data latch pulse signal output to the electrical volume
69
VOL-CLK
O
Serial data transfer clock signal output to the electrical volume
70
VOL-DATA
O
Serial data output to the electrical volume
71
POWER LED
O
LED drive signal output of power on indicator “H”: LED on
72
NC
—
Not used
73
STAND BY LED
O
LED drive signal output of standby indicator “H”: LED on
74
AVDD
—
Power supply terminal (+5V) (for A/D converter)
75
AVSS
—
Ground terminal (for A/D converter)
76
AVREF
I
Reference voltage (+5V) input terminal (for A/D converter)
77 to 80
NC
—
Not used
81
AUDIO DEC
I
Auto analog input level detection signal input terminal
82
KEY1
I
Top panel key input terminal (A/D input)
83
V/R
I
VOLUME key input terminal (A/D input)
84
NC
—
Not used
85
DIGITAL DEC
I
Auto digital input level detection signal input terminal
86 to 89
NC
—
Not used
90
STOP
I
AC cut detection signal input terminal
91
SIRCS
I
SIRCS signal input terminal
92
NC
—
Not used
93
INT
I
Top panel key input and sircs signal input detection signal input terminal with power save mode
94 to 97
NC
—
Not used
98
CO-S/MUTE
O
Soft muting on/off control signal output to the CODEC “H”: muting on
99
CO-PD
O
System reset signal output to the CODEC “L”: reset
100
CO-CS
O
Chip select signal output to the CODEC “L” active
30
SS-US501/SW-US501/UZ-US501
DIGITAL BOARD IC808 CXD9617R (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
XRST
I
System reset signal input from the system controller “L”: reset
3
EXTIN
I
Master clock signal input terminal Not used
4
FS2
I
Sampling frequency selection signal input terminal Not used
5
VDDI
—
Power supply terminal (+2.5V)
6
FS1
I
Sampling frequency selection signal input terminal Not used
7
PLOCK
O
Internal PLL lock signal output terminal Not used
8
VSS
—
Ground terminal
9
MCLK1
I
System clock input terminal (13.5 MHz)
10
VDDI
—
Power supply terminal (+2.5V)
11
VSS
—
Ground terminal
12
MCLK2
O
System clock output terminal (13.5 MHz)
13
MS
I
Master/slave setting terminal “L”: internal clock, “H”: external clock
Fixed at “L” in this set
Fixed at “L” in this set
14
SCKOUT
O
Internal system clock signal output to the CODEC
15
LRCKI1
I
L/R sampling clock signal input terminal Not used
16
VDDE
—
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal input terminal Not used
18
SDI1
I
Audio serial data input from the CODEC
19
LRCKO
O
L/R sampling clock signal output to the CODEC
20
BCKO
O
Bit clock signal output to the CODEC
21
VSS
—
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23 to 25
SDO1 to SDO3
O
Audio serial data output to the CODEC
26
SDO4
O
Audio serial data output terminal Not used
27
SPDIF
O
SPDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal input from the digital audio interface receiver
29
BCKI2
I
Bit clock signal input from the digital audio interface receiver
30
SDI2
I
Audio serial data input from the digital audio interface receiver
31
VSS
—
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Serial data input from the system controller
34
HCLK
I
Serial data transfer clock signal input from the system controller
35
HDOUT
O
Serial data output to the system controller
36
HCS
I
Chip select input from the system controller
37
SDCLK
O
SD-RAM clock signal output terminal Not used
38
CLKEN
O
SD-RAM chip enable output terminal Not used
39
RAS
O
Row address strobe signal output terminal Not used
40
VDDI
—
Power supply terminal (+2.5V)
41
VSS
—
Ground terminal
42
CAS
O
Column address strobe signal output terminal Not used
43
DQM/OE0
O
Output terminal of data input/output mask Not used
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
—
Power supply terminal (+3.3V)
31
SS-US501/SW-US501/UZ-US501
Pin No.
Pin Name
I/O
Description
47
WMD1
I
External memory wait mode setting terminal Fixed at “H” in this set
48
VSS
—
Ground terminal
49
WMD0
I
External memory wait mode setting terminal Fixed at “H” in this set
50
PAGE2
O
External memory page selection signal output terminal Not used
51
VSS
—
Ground terminal
52, 53
PAGE1, PAGE0
O
External memory page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
BTACT
O
Boot mode state display signal output terminal Not used
56
BST
I
Boot strap signal input from the system controller
57
MOD1
I
Operation mode setting terminal “L”: enhanced mode, “H”: normal mode
Fixed at “H” in this set
Fixed at “H” in this set
58
MOD0
I
Operation mode setting terminal “L”: single chip mode, “H”: can not use
Fixed at “L” in this set
Fixed at “L” in this set
59
EXLOCK
I
Error state input from the digital audio interface receiver
60
VDDI
—
Power supply terminal (+2.5V)
61
VSS
—
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
I
L/R sampling clock signal input terminal
68
GP9
O
Auto detect state output to the system controller
69
GP8
I
Channel status bit 1 input from the digital audio interface receiver
70
VDDI
—
Power supply terminal (+2.5V)
71
VSS
—
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
—
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
—
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simplicity emulation data output terminal Not used
87
TMS
I
Simplicity emulation data input start and end terminal Not used
88
XTRST
I
Simplicity emulation non-sync break signal input terminal Not used
89
TCK
I
Simplicity emulation clock signal input terminal Not used
90
TDI
I
Simplicity emulation data input terminal Not used
91
VSS
—
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
—
Power supply terminal (+2.5V)
101
VSS
—
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
—
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
—
Ground terminal
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL initialize signal input from the system controller
114, 115
SDI3, SDI4
I
Audio serial data input terminal Not used
32
SS-US501/SW-US501/UZ-US501
Pin No.
Pin Name
I/O
Description
116
SYNC
I
Sync/non-sync setting terminal “L”: sync, “H”: non-sync Fixed at “H” in this set
117 to 119
VSS
—
Ground terminal
120
VDDI
—
Power supply terminal (+2.5V)
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