Sony SS-US501 / SW-US501 / UZ-US501 Service Manual ▷ View online
25
SS-US501/SW-US501/UZ-US501
– AMP Board –
IC901
STR-F6424 (US Model)
1
O.C.P/F.B
2
S
3
D
4
VIN
5
GND
DRIVE
O.S.C
LATCH
O.V.P
START
REG.
T.S.D
1
O.C.P/F.B
2
S
3
D
4
VIN
5
GND
DRIVE
O.S.C
LATCH
O.V.P
START
REG.
ICONST
T.S.D
IC901
STR-F6676 (Except US Model)
IC905
SI-8050JF
OVER
CURRENT
PROTECTOR
LATCH
&
DRIVER
OVER HEAT
PROTECTOR
REGULATOR
+
–
–
+
–
–
RESET
VREF
COMPARATOR
ERROR AMP
OSC
1
VIN
2
SW OUT
3
GND
4
VOS
5
S.S
26
SS-US501/SW-US501/UZ-US501
• IC Pin Function Description
DIGITAL BOARD IC501 TUSB3200ACPAH (USB CODEC)
Pin No.
Pin Name
I/O
Description
1
PLLFILO
O
PLL loop filter output terminal
2
AVDD
—
Power supply terminal (+3.3V) (analog system)
3
PWMO
O
PWM signal output terminal Not used
4
PLLO
O
PLL signal output terminal Not used
5
DVSS
—
Ground terminal (digital system)
6
PUR
O
USB data (+) output terminal
7
DP
I
USB data (+) input terminal
8
DM
I
USB data (–) input terminal
9
DVDD
—
Power supply terminal (+3.3V) (digital system)
10
MRST
I
Master reset signal input from the reset signal generator “L”: reset
11
TEST
I
Input terminal for the test mode
12
EXTEN
I
Input terminal for the external MCU mode
13
RSTO
O
Reset signal output terminal Not used
14
P3.0
—
Not used
15
P3.1
O
Master clock frequency selection signal output to the digital audio transmitter
16
DVSS
—
Ground terminal (digital system)
17
XINT
I
External interrupt signal input terminal “L” active Not used
18
P3.3
—
Not used
19
P3.4
O
Generation status signal output to the digital audio transmitter
20
P3.5
—
Not used
21
DVDD
—
Power supply terminal (+3.3V) (digital system)
22
NC
—
Not used
23
PLLO
O
PLL output enable signal output terminal Not used
24
P1.0
O
Master clock frequency selection signal output to the digital audio transmitter
25, 26
P1.1, P1.2
—
Not used
27
DVDD5
—
Power supply terminal (+5V) (digital system)
28 to 32
P1.3 to P1.7
—
Not used
33
DVSS
—
Ground terminal (digital system)
34
BCK
O
Audio serial data transfer clock signal output to the digital audio transmitter
35
LRCK
O
Frame sync signal output to the digital audio transmitter
36
DOUT1
O
Audio serial data output to the digital audio transmitter
37
DVDD
—
Power supply terminal (+3.3V) (digital system)
38
DOUT2
I
Audio serial data input terminal Not used
39
CRESET
O
Reset signal output terminal Not used
40
SDIN1
O
Secondary channel enable signal output terminal Not used
41
SDA
I/O
Two-way data bus with the EEPROM
42
SCL
O
Serial data transfer clock signal output to the EEPROM
43
DVDD5
—
Power supply terminal (+5V) (digital system)
44
MCLKO
O
Master clock signal output to the digital audio transmitter
45
MCLKO2
O
Master clock signal output terminal Not used
46
DVSS
—
Ground terminal (digital system)
47, 48
MCLKI, MCLKI2
I
Master clock signal input terminal Not used
49
AVSS
—
Ground terminal (analog system)
50
XTALO
O
System clock output terminal (6 MHz)
51
XTALI
I
System clock input terminal (6 MHz)
52
PLLFILI
I
PLL loop filter input terminal
27
SS-US501/SW-US501/UZ-US501
DIGITAL BOARD IC502 DIT4096IPWR (DIGITAL AUDIO TRANSMITTER)
Pin No.
Pin Name
I/O
Description
1
CSS
I
Channel status data input terminal Not used
2
COPY/C
I
Copy protect signal or channel status serial data input terminal Not used
3
L
I
Generation status signal input from the USB CODEC
4, 5
CLK1, CLK0
I
Master clock frequency selection signal input from the USB CODEC
6
MCLK
I
Master clock signal input from the USB CODEC
7
VIO
—
Power supply terminal (+3.3V) (digital system)
8
DGND
—
Ground terminal (digital system)
9, 10
FMT0, FMT1
I
Audio data format control signal input terminal Not used
11
SCLK
I
Audio serial data transfer clock signal input from the USB CODEC
12
SYNC
I
Frame sync signal input from the USB CODEC
13
SDATA
I
Audio serial data input from the USB CODEC
14
M/S
I
Master/slave setting terminal “L”: slave, “H”: master Fixed at “L” in this set
15
RST
I
Reset signal input terminal “L”: reset
16
DGND
—
Ground terminal (digital system)
17
TX–
O
Audio serial data output terminal Not used
18
TX+
O
Audio serial data output to the digital audio interface receiver
19
VDD
—
Power supply terminal (+5V) (digital system)
20
MDAT
I
Channel status data selection signal input terminal Not used
21
MONO
I
Monoral/stereo mode selection signal input terminal “L”: stereo, “H”: monoral Not used
22
AUDIO
I
Audio data status signal input terminal “L” active Not used
23
EMPH
I
Pre-emphasis status signal input terminal “L” active Not used
24
BLSH
I
Block start mode control signal input terminal Not used
25
BLS
I/O
Block start signal input/output terminal Not used
26
V
I
Validity data input terminal Not used
27
U
I
User data input terminal Not used
28
MODE
I
Input terminal for the setting mode
28
SS-US501/SW-US501/UZ-US501
DIGITAL BOARD IC802
µ
PD783033BYGF-M53-3BA-A (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
CO-DI
O
Serial data output to the CODEC
2
CO-CLK
O
Serial data transfer clock signal output to the CODEC
3 to 5
NC
—
Not used
6
DSP-DO
I
Serial data input from the audio DSP
7
DIG-DI
O
Serial data output to the digital audio interface receiver and audio DSP
8
DIG-CLK
O
Serial data transfer clock signal output to the digital audio interface receiver and audio DSP
9
EVDD
—
Power supply terminal (+3.3V) (for input/output port)
10
EVSS
—
Ground terminal (for input/output port)
11
DSP-RST
O
System reset signal output to the audio DSP “L”: reset
12
DSP-PM
O
PLL initialize signal output to the audio DSP
13
DSP-CS
O
Chip select signal output to the audio DSP
14
DSP-HACN
I
Acknowledge signal input from the audio DSP
15
DSP-BST
O
Boot strap signal output to the audio DSP
16
DSP-GP9
I
Auto detect state input from the audio DSP
17
DSP-PLOCK
I
Internal PLL lock signal input from the audio DSP
18
DIR-ERR
I
Error state input from the digital audio interface receiver
19
DIR-CE
O
Chip enable signal output to the digital audio interface receiver
20
DIR-XST
I
Source clock selection monitor input from the digital audio interface receiver
21
VPP
—
Not used
22
DIR-AD
I
Analog/digital selection signal input from the digital audio interface receiver
23
DIR-XMODE
O
System reset signal output to the digital audio interface receiver “L”: reset
24
DIR-DO
I
Serial data input from the digital audio interface receiver
25, 26
NC
—
Not used
27
MUTE-FL, FR
O
Line muting on/off control signal output terminal (for front L-ch and R-ch) “H”: muting on
28
MUTE-
SL, SR, C
O
Line muting on/off control signal output terminal (for surround L-ch and R-ch, center)
“H”: muting on
“H”: muting on
29
MUTE-SW
O
Line muting on/off control signal output terminal (for sub woofer) “H”: muting on
30 to 33
NC
—
Not used
34
RESET
I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
35
X1
I
Sub system clock input terminal Not used
36
X2
O
Sub system clock output terminal Not used
37
NC
—
Not used
38
X2
O
Main system clock output terminal (16 MHz)
39
X1
I
Main system clock input terminal (16 MHz)
40
VSS
—
Ground terminal
41
VDD
—
Power supply terminal (+5V)
42, 43
NC
—
Not used
44
AMP-MUTE
O
Muting on/off control signal output to the amplifier circuit “H”: muting on
45
NC
—
Not used
46
P-CONT
O
Power on/off control signal output terminal “H”: power on
47 to 52
NC
—
Not used
53
LCD-CLK
O
Serial data transfer clock signal output to the LCD driver
54
LCD-DATA
O
Serial data output to the LCD driver
55
LCD-C/D
O
Clear signal output to the LCD driver “L”: clear
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