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Model
SCD-XE670
Pages
87
Size
6.12 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
scd-xe670.pdf
Date

Sony SCD-XE670 Service Manual ▷ View online

65
SCD-XE670
Pin No.
Pin Name
I/O
Description
57
VDD
Power supply terminal (+3.3V) (digital system)
58
DSAR
O
DSD data (front R-ch) output to the digital filter (IC301)
59
GND
Ground terminal (digital system)
60
DSALS
O
DSD data (surround L-ch) output to the digital filter (IC302)
61
GND
Ground terminal (digital system)
62
DSARS
O
DSD data (surround R-ch) output to the digital filter (IC302)
63
VDD
Power supply terminal (+3.3V) (digital system)
64
DSAC
O
DSD data (center) output to the digital filter (IC303)
65
GND
Ground terminal (digital system)
66
DSASW
O
DSD data (sub woofer) output to the digital filter (IC303)
67
GND
Ground terminal (digital system)
68
PHREFI
I
Phase reference signal input terminal for DSD output phase modulation
69
PHREFO
O
Phase reference signal output for DSD output phase modulation to the digital filter (IC301 to 
IC303)
70
BCKASL
I
Input/output selection signal input terminal of bit clock signal (2.8224 MHz) for DSD data output  
“L”: input (slave), “H”: output (master) (fixed at “L” in this set)
71
BCKAO
O
Bit clock signal (2.8224 MHz) output terminal for DSD data output    Not used (open)
72
BCKAI
I
Bit clock signal (2.8224 MHz) input terminal for DSD data output    Not used
73, 74
TESTO
O
Output terminal for the test    Not used
75
VDD
Power supply terminal (+3.3V) (digital system)
76
GND
Ground terminal (digital system)
77
TESTI
I
Input terminal for the test (normally: fixed at “L”)
78
TESTI
I
Input terminal for the test    Not used
79
XSBSL2
I
HD mode selection signal input from the I/O expander (IC902)
80, 81
TESTI
I
Input terminal for the test    Not used
82
XABSL1
I
HD mode selection signal input from the I/O expander (IC902)
83, 84
TESTO
O
Output terminal for the test    Not used
85
DVCKI
I
11.2896 MHz clock signal input terminal 
86
TESTI
I
Input terminal for the test    Not used
87
GND
Ground terminal (digital system)
88
MCKI
I
Master clock signal (33.8688 MHz) input terminal 
89
VDD
Power supply terminal (+3.3V) (digital system)
90
LRCK
O
L/R sampling clock signal (44.1kHz) output to the digital filter (IC301 to IC303)
91
CDDATAR
O
Serial data output terminal    Not used (open)
92
CDDATAL
O
Serial data output to the digital filter (IC301)
93
CDDATASL
I
CD mode selection signal input from the I/O expander (IC902)
94
BCKI
I
Bit clock signal (2.8224 MHz) input from the CXD3068Q (IC509) 
95
LRCKI
I
L/R sampling clock signal (44.1 kHz) input from the CXD3068Q (IC509) 
96
CDDATAI
I
Serial data input from the CXD3068Q (IC509) 
97
TESTI
I
Input terminal for the test (normally: fixed at “L”)
98
SMUTE
I
Muting on/off signal input from the CPU (IC901)    “H”: muting on
99
XRST
I
Reset signal input from the I/O expander (IC902)    “L”: reset
100
GND
Ground terminal (digital system)
66
SCD-XE670
 MAIN BOARD  IC901 CXP973F064-210R (CPU)
Pin No.
Pin Name
I/O
Description
1
MODE DF
O
SACD/CD mode selection signal output to the muting circuit
“L”: CD mode, “H”: SACD mode
2
AMUTE
O
Muting on/off signal output to the analog line circuit    “L”: muting on
3
DOCTRL
O
Digital out on/off control signal output to the CXD3068Q (IC509)
“L”: digital out off, “H”: digital out on
4
LAT DAC
O
Serial data latch pulse signal output to the D/A converter    Not used (open)
5
DATA DAC
O
Serial data output to the D/A converter    Not used (open)
6
CLK DAC
O
Serial data transfer clock signal output to the D/A converter    Not used (open)
7
FCS JMP 1
O
Focus jump 1 signal output to the BA5983FP (IC502)
8
FCS JMP 2
O
Focus jump 2 signal output to the BA5983FP (IC502)
9
SENS CD
I
Internal status (SENSE) signal input from the CXD3068Q (IC509)
10
XCS DRAM
O
Chip select signal output to the D-RAM    Not used (pull up)
11
XCS IO
O
Chip select signal output to the I/O expander (IC902)
12
XCS DVD
O
Chip select signal output to the CXD1882R (IC701)
13
VSS
Ground terminal (digital system)
14 to 21
D0 to D7
I/O
Two-way data bus with the CXD1882R (IC701)  and I/O expander (IC902)
22
INT0 DVD
I
Interrupt signal input from the CXD1882R (IC701)
23
INT1 DVD
I
Interrupt signal input from the CXD1882R (IC701)
24
T SENS
I
Disc tray status detection signal input terminal    Not used (open)
25
MON DVD
I
Monitor signal input terminal    Not used (open)
26
DATA CD
O
Serial data output to the CXD3068Q (IC509)
27
XLAT CD
O
Serial data latch pulse signal output to the CXD3068Q (IC509)
28
A1IN
I
Control A1 signal input terminal    Not used (fixed at “H”)
29
COUT CD
I
Numbers of track counted signal input from the CXD3068Q (IC509)
30
IN SW
I
Loading in switch (S152) input terminal    “L”: loading in
31
OUT SW
I
Loading out switch (S151) input terminal    “L”: loading out
32
MIRR RF
I
Mirror signal input from the CXD3068Q (IC509)
33
SUBQ CD
I
Subcode Q data input from the CXD3068Q (IC509)
34
SCOR CD
I
Subcode sync (S0+S1) detection signal input from the CXD3068Q (IC509)
35
SQCLK CD
O
Subcode Q data reading clock signal output to the CXD3068Q (IC509)
36
Not used (open)
37
CLOK CD
O
Serial data transfer clock signal output to the CXD3068Q (IC509)
38
XRST
I
System reset signal input from the reset signal generator (IC905)    “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
39
VSS
Ground terminal (digital system)
40
XTAL I
System clock input terminal (20 MHz)
41
EXTAL O
System clock output terminal (20 MHz)
42
VDD
Power supply terminal (+3.3V) (digital system)
43
SPDA
O
Spindle motor (M3) control signal output to the BA5912AFP (IC512)
44
APDO
O
Output terminal for offset adjustment of APEO (<z/. pin of CXD1882R (IC701))
45
MUTE DSD
O
Muting on/off signal output to the DSD decoder (IC801) and CXD9647R (IC803)
“H”: muting on
46
XMSLAT
O
Serial data latch pulse signal output to the DSD decoder (IC801)
47
READY DSD
I
Ready signal input from the DSD decoder (IC801) and CXD9647R (IC803)    “L”: ready
48
SDIN DSD
I
Serial data input from the DSD decoder (IC801) and CXD9647R (IC803)
49
SOUT DSD
O
Serial data output to the DSD decoder (IC801) and CXD9647R (IC803)
50
SCK DSD
O
Serial data transfer clock signal output to the DSD decoder (IC801) and CXD9647R (IC803)
67
SCD-XE670
Pin No.
Pin Name
I/O
Description
51
LD ON
O
Laser diode on/off control signal output to the CXD1881R (IC001)
“L”: laser diode off, “H”: laser diode on
52
XDIS IO
O
Reset signal output to the I/O expander (IC902)    “L”: reset
53
SDOUT
O
Serial data output to the MSM9202 (IC801)
54
SLK
O
Serial data transfer clock signal output to the MSM9202 (IC801)
55
VSS
Ground terminal (digital system)
56
REQ
O
Request signal output to the MSM9202 (IC801)
57
FCS BST
O
Focus boost signal output terminal    Not used (open)
58
GFS DVD
I
Guard frame sync signal input from the CXD1882R (IC701)
59
LED DRV
O
LED drive signal output of the multi-channel indicator (D803)    “H”: LED on
60
KEY 0
I
Key input terminal (A/D input)    S807 to S809 (H, X, x) keys input
61
KEY 1
I
Key input terminal (A/D input)
S801 to S805 (m, M, MENU, SACD/CD, MILTI/2CH) keys input
62
KEY 2
I
Key input terminal (A/D input)    S810 to S814, S830 (TIME/TEXT, PLAY MODE, CHECK, 
CLEAR, REPEAT, PUSH ENTER) keys input
63
KEY 3
I
Key input terminal (A/D input)    S806 (OPEN/CLOSE A) key input
64
JITTER
I
Jitter signal input
65
TE
I
Tracking error signal input from the CXD1881R (IC001)
66
SP ERR
I
Spindle motor backward voltage input terminal
67
FE/PI
I
Focus error signal input from the CXD1881R (IC001)
68
AVSS
Ground terminal (for A/D converter)
69
AVREF
I
Reference voltage input terminal (for A/D converter)
70
AVDD
Power supply terminal (+3.3V) (for A/D converter)
71
GFS CD
I
Guard frame sync signal input from the CXD3068Q (IC509)
72
SCLK CD
O
SENSE serial data reading clock signal output to the CXD3068Q (IC509)
73
1/2 LD
Not used (open)
74
FOK CD
I
Focus OK signal input from the CXD3068Q (IC509)
75
LOCK CD
I
GFS is sampled by 460 Hz    “H” input when GFS is “H”
76
XRF AD CE
O
Chip enable signal output to the A/D converter    Not used (open)
77
SDCLK RF
O
Serial data transfer clock signal output to the CXD1881R (IC001)
78
EEPSIO
I/O
Two-way data bus with the EEPROM (IC903)
79
EEPSCL
O
Clock signal output to the EEPROM (IC903)
80
RXD
I
Serial data input from the RS-232C (for check)
81
TXD
O
Serial data output to the RS-232C (for check)
82
RM
I
Remote control signal input from the remote control receiver (IC802)
83
SDATA RF
I/O
Two-way data bus with the CXD1881R (IC001)
84
XWR
O
Write strobe signal output to the CXD1882R (IC701) and I/O expander (IC902)
85
XRD
O
Read strobe signal output to the CXD1882R (IC701) and I/O expander (IC902)
86
NC
Not used (fixed at “H” )
87
VDD
Power supply terminal (+3.3V)  (digital system)
88
VSS
Ground terminal (digital system)
89 to 91
A0 to A2
O
Address signal output to the CXD1882R (IC701) and I/O expander (IC902)
92 to 96
A3 to A7
O
Address signal output to the CXD1882R (IC701)
97
INIT DF
O
Initial signal output to the digital filter    Not used
98
LATCH DF
O
Latch signal output to the digital filter (IC301 to IC303)
99
SHIFT DF
O
Shift signal output to the digital filter (IC301 to IC303)
100
SCDATA DF
O
Serial data output to the digital filter (IC301 to IC303)
68
SCD-XE670
 MAIN BOARD  IC902  CXD1095BR (I/O EXPANDER)
Pin No.
Pin Name
I/O
Description
1
MUT CD
O
Muting on/off control signal output to the CXD3068Q (IC509)    “L”: muting on
2
MUT 2D
O
Muting control signal output to the BA5983FP (IC502)
3
MUT LOAD
O
Muting control signal output to the BA5912AFP (IC512)
4
SP ON
O
Muting control signal output to the BA5912AFP (IC512)
5
PB5
Not used (open)
6
TBLL
O
Table motor drive signal (counterclockwise direction) output terminal    Not used (pull up)
7
TBLR
O
Table motor drive signal (clockwise direction) output terminal    Not used (pull up)
8
VSS
Ground terminal (digital system)
9
PC0
Not used (open)
10
D SENS
I
Disc status detection signal input terminal    Not used (fixed at “L”) 
11, 12
S1, S2
I
Disc tray position detection signal input terminal    Not used (fixed at “H”) 
13
LOAD OUT
O
Loading motor drive signal (loading out direction) output to the BA5912AFP (IC512)
14
PC5
Not used (open)
15
LOAD IN
O
Loading motor drive signal (loading in direction) output to the BA5912AFP (IC512)
16
A1OUT
O
Control A1 signal output terminal    Not used (open)
17
NC
Not used (open)
18
RST DSD
O
Reset signal output to the DSD decoder (IC801) and CXD9647R (IC803)    “L”: reset
19
RST DP
O
Reset signal output to the MSM9202 (IC801)    “L”: reset
20
RST DVD
O
Reset signal output to the CXD1882R (IC701)    “L”: reset
21
RST CD
O
Reset signal output to the CXD3068Q (IC509)    “L”: reset
22
VMOD
O
Power on/off control signal output for modulation circuit on optical pick-up block
“L”: power off, “H”: power on
23
VSS
Ground terminal (digital system)
24
VDD
Power supply terminal (+3.3V) (digital system)
25
MULTI
O
Multi/2ch selection signal output    “L”: 2ch, “H”: multi
26
SDEN
O
Serial data enable signal output to CXD1881R (IC001)
27
ISBTEST
O
Output terminal for disc inspection mode to DSD decoder (IC801)
28 to 30
D0 to D2
I/O
Two-way data bus with the CXD1882R (IC701) and the CPU (IC901)
31, 32
NC
Not used (open)
33 to 37
D3 to D7
I/O
Two-way data bus with the CXD1882R (IC701) and the CPU (IC901)
38
XCLR
I
Clear signal input terminal        Not used (fixed at “H”)
39
XDIS
I
Reset signal input from the CPU (IC901)    “L”: reset
40
VSS
Ground terminal (digital system)
41
XWR
I
Write strobe signal input from the CPU (IC901)
42
XRD
I
Read strobe signal input from the CPU (IC901)
43
XCS
I
Chip select signal input from the CPU (IC901)
44 to 46
A0 to A2
I
Address signal input from the CPU (IC901) 
47, 48
PE0, PE1
Not used (open)
49
NC
Not used (open)
50
PE2
Not used (open)
51
CDMODESEL
O
CD mode selection signal output to the CXD9647R (IC803)
52
HDMODESEL
O
HD mode selection signal output to the CXD9647R (IC803)
53
XZLAT
O
Serial data latch pulse signal output to the CXD9647R (IC803)
54
CD SACD
O
SACD/CD mode selection signal output terminal    Not used
55
VSS
Ground terminal (digital system)
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