Sony SCD-XA9000ES Service Manual ▷ View online
89
SCD-XA9000ES
Pin No.
Pin Name
I/O
Description
55
HRDY
O
Ready signal output to the i-link system controller
56
DVDD (3.3V)
—
Power supply terminal (+3.3V)
57
VSS
—
Ground terminal
58
HD0
I/O
Two-way data bus with the i-link system controller
59, 60
BDX0, BDX2
O
Serial data output terminal Not used
61
IACK
O
Interrupt acknowledge signal output terminal Not used
62
HBIL
I
Byte identification signal input from the i-link system controller
63
NMI
I
Non-maskable interrupt input terminal Not used
64, 65
INT0, INT1
I
Interrupt signal input terminal Not used
66
INT2
I
Interrupt signal input from the HINT (ta pin)
67
INT3
I
Interrupt signal input terminal Not used
68
CVDD (1.8V)
—
Power supply terminal (+1.8V)
69
HD1
I/O
Two-way data bus with the i-link system controller
70
VSS
—
Ground terminal
71
BCLKX1
I
Transmit clock signal input terminal Not used
72
VSS
—
Ground terminal
73
BFSX1
I
Frame sync signal input terminal Not used
74
BDX1
O
Serial data output terminal Not used
75
DVDD (3.3V)
—
Power supply terminal (+3.3V)
76
VSS
—
Ground terminal
77 to 79
CLKMD1 to
CLKMD3
I
Clock mode selection signal input terminal Not used
80
HPI16
I
HPI 16 bit selection signal input terminal Not used
81
HD1
I/O
Two-way data bus with the i-link system controller
82
TOUT
O
Timer output terminal Not used
83
EMU0
I
Not used
84
EMU1/OFF
I
Not used
85
TDO
O
Not used
86
TDI
I
Not used
87
TRST
I
Not used
88
TCK
I
Not used
89
TMS
I
Not used
90
VSS
—
Ground terminal
91
CVDD (1.8V)
—
Power supply terminal (+1.8V)
92
HPIENA
I
HPI module selection signal input terminal Not used
93
VSS
—
Ground terminal
94
CLKOUT
O
Master clock signal output terminal Not used
95
HD3
I/O
Two-way data bus with the i-link system controller
96
X1
O
System clock output terminal (20 MHz)
97
X2/CLKIN
I
System clock input terminal (20 MHz)
98
RS
I
Reset signal input from the i-link system controller “L”: reset
99 to 104
D0 to D5
I/O
Two-way data bus terminal Not used
105
A16
O
Address signal output terminal Not used
106
VSS
—
Ground terminal
107 to 110
A17 to A20
O
Address signal output terminal Not used
111
VSS
—
Ground terminal
112
DVDD (3.3V)
—
Power supply terminal (+3.3V)
90
SCD-XA9000ES
Pin No.
Pin Name
I/O
Description
113 to 119
D6 to D12
I/O
Two-way data bus terminal Not used
120
HD4
I/O
Two-way data bus with the i-link system controller
121 to 123
D13 to D15
I/O
Two-way data bus terminal Not used
124
HD5
I/O
Two-way data bus with the i-link system controller
125
CVDD (1.8V)
—
Power supply terminal (+1.8V)
126
VSS
—
Ground terminal
127
HDS1
I
Data strobe signal input from the i-link system controller
128
VSS
—
Ground terminal
129
HDS2
I
Data strobe signal input from the i-link system controller
130
DVDD (3.3V)
—
Power supply terminal (+3.3V)
131 to 134
A0 to A3
O
Address signal output terminal Not used
135
HD6
I/O
Two-way data bus with the i-link system controller
136 to 141
A4 to A9
O
Address signal output terminal Not used
142
CVDD (1.8V)
—
Power supply terminal (+1.8V)
143
A21
O
Address signal output terminal Not used
144
VSS
—
Ground terminal
91
SCD-XA9000ES
•
LINK BOARD IC1903 M30626FHPFP-SCD-XA9000 (I-LINK SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1 to 7
HD6 to HD0
I/O
Two-way data bus with the i-link DSP
8
BYTE
I
External data bus line byte selection signal input terminal
“L”: 16 bit, “H”: 8 bit Fixed at “L” in this set
“L”: 16 bit, “H”: 8 bit Fixed at “L” in this set
9
CNVSS
—
Processor mode selection signal input terminal “L”: single Fixed at “L” in this set
10, 11
NC
O
Not used
12
RESET
I
Reset signal input from the CPU “L”: reset
13
XOUT
O
System clock output terminal (10 MHz)
14
VSS
—
Ground terminal
15
XIN
I
System clock input terminal (10 MHz)
16
VCC
—
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt input terminal Not used
18
NC
O
Not used
19
AKE_XF
I
External flag signal input from the i-link DSP
20
NC
O
Not used
21
HRDY
I
Ready signal input from the i-link DSP
22
XHAS
O
Address strobe signal output to the i-link DSP
23, 24
XHDS1, XHDS2
O
Data strobe signal output to the i-link DSP
25
XHCS
O
Chip select signal output to the i-link DSP
26
XRS
O
Reset signal output to the i-link DSP “L”: reset
27, 28
NC
O
Not used
29
IIC CLK
I/O
Clock signal bus with the CPU and EEPROM
30
IIC DATA
I/O
Two-way data bus with the CPU and EEPROM
31
TXD1
I
Not used
32
RXD1
I
Not used
33
CLK1
I
Not used
34
RTS1
I
Not used
35 to 38
NC
O
Not used
39
RDY
I
Ready signal input from the i-link interface
40
ALE
O
Not used
41
HOLD
I
Not used
42
HLDA
O
Not used
43
BCLK
O
Not used
44
RD
O
Read data output to the i-link interface and EEPROM
45
WRH
O
Not used
46
WR
O
Write data output to the i-link interface and EEPROM
47
NC
O
Not used
48
EEP_CS
O
Chip select signal output to the EEPROM
49
CS1
O
Chip select signal output to the i-link interface
50
NC
O
Not used
51, 52
HCNTL0, HCNTL1
O
Control signal output to the i-link DSP
53
HBIL
O
Byte identification signal output to the i-link DSP
54
HRW
O
Read/write signal output to the i-link DSP
55, 56
NC
O
Not used
57 to 61
A13 to A9
O
Address signal output to the EEPROM
62
VCC
—
Power supply terminal (+3.3V)
63
A8
O
Address signal output to the i-link interface and EEPROM
92
SCD-XA9000ES
Pin No.
Pin Name
I/O
Description
64
GND
—
Ground terminal
65 to 71
A7 to A1
O
Address signal output to the i-link interface and EEPROM
72
A0
O
Address signal output terminal Not used
73 to 88
D15 to D0
I/O
Two-way data bus with the i-link interface and EEPROM
89
PHY_BIAS
O
Power down signal output to the i-link interface
90
PHY_RST
O
Power reset signal output to the i-link interface “L”: reset
91
NC
O
Not used
92
LINK_RST
O
Link reset signal output to the i-link interface “L”: reset
93 to 95
NC
O
Not used
96
AVSS
—
Ground terminal (for A/D converter)
97
NC
O
Not used
98
A/D VREF
I
Reference voltage (+3.3V) input terminal (for A/D converter)
99
AVCC 3.3V
—
Power supply terminal (+3.3V) (for A/D converter)
100
HD7
I/O
Two-way data bus with the i-link DSP
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