Sony SCD-XA9000ES Service Manual ▷ View online
85
SCD-XA9000ES
•
MAIN BOARD IC901 CXP973064-241R (CPU)
Pin No.
Pin Name
I/O
Description
1
MUTE_ LOAD
O
Muting on/off control signal output to the loading motor drive “L”: muting on
2
RST_DY
O
Reset signal output to the DSD digital signal processor “L”: reset
3
DOCTRL
O
Digital out on/off control signal output to the digital signal processor
“L”: digital out off, “H”: digital out on
“L”: digital out off, “H”: digital out on
4
MUTE_2D
O
Muting on/off control signal output to the focus/tracking coil drive “L”: muting on
5
MODE_SACD
O
SACD/CD mode selection signal output terminal “L”: CD mode, “H”: SACD mode
6
SP_ON
O
Muting on/off control signal output to the spindle motor drive “L”: muting on
7
FCS_JMP1
O
Focus jump 1 signal output terminal
8
FCS_JMP2
O
Focus jump 2 signal output terminal
9
SENS_CD
I
Internal status (SENSE) signal input from the digital signal processor
10
XDIS_IO
O
Reset signal output to the I/O expander “L”: reset
11
XCS_IO
O
Chip select signal output to the I/O expander
12
XCS_DVD
O
Chip select signal output to the SACD decoder
13
VSS
—
Ground terminal (digital system)
14 to 21
D0 to D7
I/O
Two-way data bus with the SACD decoder and I/O expander
22
INT0_DVD
I
Interrupt signal input from the SACD decoder
23
INT1_DVD
I
Interrupt signal input from the SACD decoder
24
T_SENS
I
Input terminal of disc tray status detection signal from table sensor Not used
25
MIRR_RF
I
Mirror signal input from the digital signal processor
26
SCOR_CD
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
27
RDY_DSD
I
Ready signal input from the DSD decoder “L”: ready
28
MUTE_DSD
O
Soft muting on/off control signal output to the DSD decoder “H”: muting on
29
COUT_CD
I
Numbers of track counted signal input from the digital signal processor
30
IN_SW
I
Loading in switch input terminal “L”: loading in
31
OUT_SW
I
Loading out switch input terminal “L”: loading out
32
—
I
Not used
33
SQSO_CD
I
Subcode Q data input from the digital signal processor
34
DATA_CD
O
Serial data output to the digital signal processor
35
CLOK_CD
O
Serial data transfer clock signal output to the digital signal processor
36
XLAT_CD
O
Serial data latch pulse signal output to the digital signal processor
37
SQCK_CD
O
Subcode Q data reading clock signal output to the digital signal processor
38
XRST
I
System reset signal input terminal “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
39
VSS
—
Ground terminal (digital system)
40
XTAL I
System clock input terminal (20 MHz)
41
EXTAL O
System clock output terminal (20 MHz)
42
VDD
—
Power supply terminal (+3.3V) (digital system)
43
SPDA
O
Spindle motor control signal output terminal
44
APDO
O
Output terminal for offset adjustment of APEO (<z/. pin of SACD decoder)
45
LOAD_IN
O
Loading motor drive signal (loading in direction) output terminal
46
LOAD_OUT
O
Loading motor drive signal (loading out direction) output terminal
47
XLAT_DSD
O
Serial data latch pulse signal output to the DSD decoder
48
SIN_DSD
I
Serial data input from the DSD decoder and DSD digital signal processor
49
SOUT_DSD
O
Serial data output to the DSD decoder, DSD digital signal processor and D/A converter
50
SCK_DSD
O
Serial data transfer clock signal output to the DSD decoder, DSD digital signal processor and D/A
converter
converter
86
SCD-XA9000ES
Pin No.
Pin Name
I/O
Description
51
BUSY_DP
I
Busy signal input from the display controller
52
SIN_DP
I
Serial data input from the display controller
53
SOUT_DP
O
Serial data output to the display controller
54
SCLK_DP
O
Serial data transfer clock signal output to the display controller
55
VSS
—
Ground terminal (digital system)
56
REQ_DP
O
Request signal output to the display controller
57
XCS_DY
O
Chip select signal output to the DSD digital signal processor
58
GFS_DVD
I
Guard frame sync signal input from the SACD decoder
59
SP_ERR
I
Spindle motor backward voltage input terminal
60
AMUT_MCH
O
Surround, center and sub woofer audio muting on/off control signal output terminal
“L”: muting on
“L”: muting on
61
MLS_RST
O
Reset signal output to the i-link system controller “L”: reset
62
LAT_DF_B
O
Serial data latch pulse signal output to the D/A converter
63
DOON
O
Digital out on/off control signal output terminal “L”: digital out off, “H”: digital out on
64
JITTER
I
Jitter signal input terminal
65
TE
I
Tracking error signal input from the SACD/CD RF amplifier
66
PI
I
Pull in signal input from the SACD/CD RF amplifier
67
FE
I
Focus error signal input from the SACD/CD RF amplifier
68
AVSS
—
Ground terminal (for A/D converter)
69
AVREF
I
Reference voltage (+3.3V) input terminal (for A/D converter)
70
AVDD
—
Power supply terminal (+3.3V) (for A/D converter)
71
GFS_CD
I
Guard frame sync signal input from the digital signal processor
72
SCLK_CD
O
SENSE serial data reading clock signal output to the digital signal processor
73
MUTE_CD
O
Muting on/off control signal output to the digital signal processor “H”: muting on
74
FOK_CD
I
Focus OK signal input from the digital signal processor
75
LOCK_CD
I
GFS is sampled by 460 Hz “H” input when GFS is “H”
76
MULTI
O
Multi/2ch selection signal output terminal “L”: 2ch, “H”: multi
77
CLK_RF
O
Serial data transfer clock signal output to the SACD/CD RF amplifier
78
EEPSIO
I/O
Two-way data bus with the EEPROM and i-link system controller
79
EEPSCL
I/O
Clock signal bus with the EEPROM and i-link system controller
80
RXD
I
Not used
81
TXD
O
Not used
82
CLK_SW
I
OSC on/off control signal output terminal “L”: OSC off, “H”: OSC on
83
DATA_RF
I/O
Two-way data bus with the SACD/CD RF amplifier
84
XWR
O
Write strobe signal output to the SACD decoder and I/O expander
85
XRD
O
Read strobe signal output to the SACD decoder and I/O expander
86
NC_(PWE/VPP)
—
Not used
87
VDD
—
Power supply terminal (+3.3V) (digital system)
88
VSS
—
Ground terminal (digital system)
89
A0
O
Address signal output to the SACD decoder and I/O expander
90 to 96
A1 to A7
O
Address signal output to the SACD decoder
97
INIT_DF
O
Reset signal output to the D/A converter “L”: reset
98
LAT_DF_A
O
Serial data latch pulse signal output to the D/A converter
99
SWGUP
O
Sub woofer gain up/normal control signal output terminal “L”: normal, “H”: gain up
100
LD_ON
O
Laser diode on/off control signal output to the SACD/CD RF amplifier
“L”: laser diode off, “H”: laser diode on
“L”: laser diode off, “H”: laser diode on
87
SCD-XA9000ES
•
MAIN BOARD IC904 ISPLSI2032VE-110LT44-SA8 (I/O EXPANDER)
Pin No.
Pin Name
I/O
Description
1
SI_SEL
O
Serial data selection signal output for SIN_DSD (rk pin of CPU)
“L”: DSD decoder serial data, “H”: DSD digital signal processor serial data
“L”: DSD decoder serial data, “H”: DSD digital signal processor serial data
2
ZEROL
I
L-ch zero data flag detection signal input terminal Not used
3
FS64
O
Clock signal (2.8224 MHz) output terminal Not used
4
FS128
O
Clock signal (5.6448 MHz) output terminal Not used
5
YO
I
Clock signal (11.2896 MHz) input terminal Not used
6
VCC
—
Power supply terminal (+5V) (digital system)
7
XBSCAN
—
Not used
8
TDI
—
Not used
9
XCS
I
Chip select signal input from the CPU
10
XRD
I
Read strobe signal input from the CPU
11
XWR
I
Write strobe signal input from the CPU
12 to 16
D0 to D4
I/O
Two-way data bus with the SACD decoder and the CPU
17
GND
—
Ground terminal (digital system)
18
TDO
—
Not used
19 to 21
D5 to D7
I/O
Two-way data bus with the SACD decoder and the CPU
22
A
I
Address signal input from the CPU
23
CDPDSW
O
Photo diode for CD on/off control signal output terminal Not used
24
RST
I
Reset signal input from the CPU “L”: reset
25
RST_DSD
O
Reset signal output to the DSD decoder “L”: reset
26
RST_DP
O
Reset signal output to the diplay controller “L”: reset
27
TCK
—
Not used
28
VCC
—
Power supply terminal (+5V) (digital system)
29
XRESET
—
Not used
30
TMS
—
Not used
31
RST_DVD
O
Reset signal output to the SACD decoder “L”: reset
32
RST_CD
O
Reset signal output to the digital signal processor “L”: reset
33
VMOD
O
Photo diode on/off control signal output terminal “H”: photo diode on
34
MULTI
O
Multi/2ch selection signal output terminal Not used
35
SDEN
O
Serial data enable signal output to SACD/CD RF amplifier
36
ISBTEST
O
Output terminal for disc inspection mode to DSD decoder
37
AMUTE
O
Front and 2ch audio muting on/off control signal output terminal “L”: muting on
38
LMUTE
O
L-ch muting on/off control signal output terminal Not used
39
GND
—
Ground terminal (digital system)
40
GOE
—
Not used
41
ZEROR
I
R-ch zero data flag detection signal input terminal Not used
42
ZDFL
I
Front L-ch zero data flag detection signal input terminal Not used
43
ZDFR
I
Front R-ch zero data flag detection signal input terminal Not used
44
LIM_SW
I
Detection signal input from limit in switch The optical pick-up is inner position when “H”
88
SCD-XA9000ES
•
LINK BOARD IC1902 TMS320VC5409PGE100A (I-LINK DSP)
Pin No.
Pin Name
I/O
Description
1
VSS
—
Ground terminal
2
A22
O
Address signal output terminal Not used
3
VSS
—
Ground terminal
4
DVDD (3.3V)
—
Power supply terminal (+3.3V)
5
A10
O
Address signal output terminal Not used
6
HD7
I/O
Two-way data bus with the i-link system controller
7 to 11
A11 to A15
O
Address signal output terminal Not used
12
CVDD (1.8V)
—
Power supply terminal (+1.8V)
13
HAS
I
Address strobe signal input from the i-link system controller
14, 15
VSS
—
Ground terminal
16
CVDD (1.8V)
—
Power supply terminal (+1.8V)
17
HCS
I
Chip select signal input from the i-link system controller
18
HR/W
I
Read/write signal input from the i-link system controller
19
READY
I
Ready signal input terminal Not used
20
PS
I
Program select signal input terminal Not used
21
DS
I
Data select signal input terminal Not used
22
IS
I
I/O space select signal input terminal Not used
23
R/W
O
Read/write signal output terminal Not used
24
MSTRB
O
Memory strobe signal output terminal Not used
25
IOSTRB
O
I/O strobe signal output terminal Not used
26
MSC
O
Microstate complete signal output terminal Not used
27
XF
O
External flag signal output to the i-link system controller
28
HOLDA
O
Hold acknowledge signal output terminal Not used
29
IAQ
O
Instruction acquisition signal output terminal Not used
30
HOLD
I
Hold signal input terminal Not used
31
BIO
I
Branch control signal input terminal Not used
32
MP/MC
I
Microprocessor/microcomputer mode selection signal input terminal
“L”: microcomputer mode, “H”: microprocessor mode Fixed at “L” in this set
“L”: microcomputer mode, “H”: microprocessor mode Fixed at “L” in this set
33
DVDD (3.3V)
—
Power supply terminal (+3.3V)
34
VSS
—
Ground terminal
35
BDR1
I
Serial data input terminal Not used
36
BFSR1
I
Frame sync signal input terminal Not used
37
VSS
—
Ground terminal
38
BCLKR1
I
Receive clock signal input terminal Not used
39
HCNTL2
I
Control signal input from the i-link system controller
40
VSS
—
Ground terminal
41, 42
BCLKR0, BCLKR2
I
Receive clock signal input terminal Not used
43, 44
BFSR0, BFSR2
I
Frame sync signal input terminal Not used
45
BDR0
I
Serial data input terminal Not used
46
HCNTL1
I
Control signal input from the i-link system controller
47
BDR2
I
Serial data input terminal Not used
48, 49
BCLKX0, BCLKX2
I
Transmit clock signal input terminal Not used
50
VSS
—
Ground terminal
51
HINT
O
Interrupt signal output to the INT2 (yh pin)
52
CVDD (1.8V)
—
Power supply terminal (+1.8V)
53, 54
BFSX0, BFSX2
I
Frame sync signal input terminal Not used
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