Sony SCD-XA1200ES Service Manual ▷ View online
37
SCD-XA1200ES
MAIN BOARD IC706 CXD2754Q (SA-CD/CD DECODER)
Pin No.
Pin Name
I/O
Description
1
CKVDD
-
Power supply terminal (+1.8V) (for clock multiplier PLL)
2
CKVSS
-
Ground terminal (for clock multiplier PLL)
3
MCKI
I
System clock (11.2896 MHz) signal input terminal
4, 5
CKSEL1, CKSEL0
I
System clock setting terminal Fixed at 11.2896 MHz in this set
6
VDIOCK
-
Power supply terminal (+3.3V) (for clock I/O)
7
VSIOCK
-
Ground terminal (for clock I/O)
8
EXCKO
O
External clock output terminal Not used
9
VDC0
-
Power supply terminal (+1.8V) (for core)
10
VSC0
-
Ground terminal (for core)
11 to 18
D0 to D7
I/O
Two-way data bus with the master controller
19
VDIO0
-
Power supply terminal (+3.3V) (for I/O)
20
VSIO0
-
Ground terminal (for I/O)
21 to 29
A0 to A8
I
Address signal input from the master controller
30
VDC1
-
Power supply terminal (+1.8V) (for core)
31
VSC1
-
Ground terminal (for core)
32
XINT
O
Interrupt signal output to the master controller
33
XCS
I
Chip select signal input from the master controller
34
XWAIT
O
Wait signal output to the master controller
35
XWR
I
Write enable signal input from the master controller
36
XRD
I
Read enable signal input from the master controller
37
XRST
I
System reset signal input from the reset signal generator and master controller "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
38
TRST
I
JTAG reset signal input from the reset signal generator and master controller "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
39
TCK
I
Clock signal input terminal (for JTAG)
40
TDI
I
Test data input terminal (for JTAG)
41
TDO
O
Test data output terminal (for JTAG)
42
TMS
I
Mode selection signal input terminal (for JTAG)
43
SCANEN
I
Test terminal
44 to 47
TEST0 to TEST3
I
Test terminal
48
VDC2
-
Power supply terminal (+1.8V) (for core)
49
VSC2
-
Ground terminal (for core)
50 to 57
MNT0 to MNT7
O
Monitor terminal
58
EXMNT
O
Extra monitor terminal
59
VDIO1
-
Power supply terminal (+3.3V) (for I/O)
60
VSIO1
-
Ground terminal (for I/O)
61
SMUTE
I
Soft muting on/off control signal input from the master controller "H": muting on
62 to 69
SUPDT0 to
SUPDT7
O
Not used
70
XSUPAK
O
Not used
71
FRAME
O
SA-CD frame signal output terminal Not used
72
VDC3
-
Power supply terminal (+1.8V) (for core)
73
VSC3
-
Ground terminal (for core)
74
DSBCKAI
I
Bit clock signal input terminal (for DSD data output) Not used
75
DSBCKAO
O
Bit clock signal output terminal (for DSD data output) Not used
76
DSBCKASL
I
Bit clock signal input/output selection terminal (for DSD data output)
"L": input (slave), "H": output (master) Fixed at "H" in this set
"L": input (slave), "H": output (master) Fixed at "H" in this set
38
SCD-XA1200ES
Pin No.
Pin Name
I/O
Description
77
DSPHREFI
I
Phase reference signal input terminal (for DSD output phase modulation) Not used
78
DSPHREFO
O
Phase reference signal output to the D/A converter (for DSD output phase modulation)
79
VDDSD0
-
Power supply terminal (+3.3V) (for DSD data output)
80
VSDSD0
-
Ground terminal (for DSD data output)
81
DSADML
O
DSD data output terminal (for down mix L-ch) Not used
82
DSADMR
O
DSD data output terminal (for down mix R-ch) Not used
83
DSAL
O
DSD data output to the D/A converter (for front L-ch)
84
DSAR
O
DSD data output to the D/A converter (for front R-ch)
85
DSALS
O
DSD data output to the D/A converter (for surround L-ch)
86
DSARS
O
DSD data output to the D/A converter (for surround R-ch)
87
VDDSD1
-
Power supply terminal (+3.3V) (for DSD data output)
88
VSDSD1
-
Ground terminal (for DSD data output)
89
DSAC
O
DSD data output to the D/A converter (for center)
90
DSASW
O
DSD data output to the D/A converter (for sub woofer)
91
DSAEXTR
O
DSD data output terminal (for extra channel) Not used
92
VDC4
-
Power supply terminal (+1.8V) (for core)
93
VSC4
-
Ground terminal (for core)
94
CDLRCK
O
L/R sampling clock signal output to the D/A converter (for CD data output)
95
CDBCK
O
Bit clock signal output to the D/A converter (for CD data output)
96
PCMD1
O
CD data output to the D/A converter
97, 98
PCMD2, PCMD3
O
Decimation data output terminal Not used
99
BCK958
O
Bit clock signal output terminal Not used
100
DOUT958
O
Digital out signal output terminal
101
VDIO2
-
Power supply terminal (+3.3V) (for I/O)
102
VSIO2
-
Ground terminal (for I/O)
103 to 108
IOUT0 to IOUT5
O
DSD data output terminal (for IEEE1394 link chip) Not used
109
VDC5
-
Power supply terminal (+1.8V) (for core)
110
VSC5
-
Ground terminal (for core)
111
IANCO
O
Ancillary data output terminal (for IEEE1394 link chip) Not used
112
IFRM
O
Frame signal output terminal (for IEEE1394 link chip) Not used
113
IOUT
O
Enable signal output terminal (for IEEE1394 link chip) Not used
114
XSAK
O
Effective flag output terminal (for DVD stream data output) Not used
115
XSHD
O
Header flag output terminal (for DVD stream data output) Not used
116
IBCK
O
Bit clock signal output terminal (for IEEE1394 link chip) Not used
117
XSRQ
I
Request signal input terminal (for DVD stream data output) Not used
118
IFULL
I
Data transmission hold request signal output terminal (for IEEE1394 link chip) Not used
119
IEMPTY
I
Hi-speed transmission request signal output terminal (for IEEE1394 link chip) Not used
120
VDIO3
-
Power supply terminal (+3.3V) (for I/O)
121
VSIO3
-
Ground terminal (for I/O)
122 to 125
MA0 to MA3
O
Address signal output to the SD-RAM
126
VDC6
-
Power supply terminal (+1.8V) (for core)
127
VSC6
-
Ground terminal (for core)
128 to 134
MA4 to MA10
O
Address signal output to the SD-RAM
135
MA11
O
Address signal output terminal Not used
136
BA0
O
Bank address signal output to the SD-RAM
137
BA1
O
Bank address signal output terminal Not used
138
XRAS
O
Row address strobe signal output to the SD-RAM
39
SCD-XA1200ES
Pin No.
Pin Name
I/O
Description
139
XCAS
O
Column address strobe signal output to the SD-RAM
140
VDC7
-
Power supply terminal (+1.8V) (for core)
141
VSC7
-
Ground terminal (for core)
142
XMWR
O
Write enable signal output to the SD-RAM
143
MCKE
O
Clock enable signal output to the SD-RAM
144
MMCK
O
Clock signal output to the SD-RAM
145
VDIO4
-
Power supply terminal (+3.3V) (for I/O)
146
VSIO4
-
Ground terminal (for I/O)
147
LDQM
O
Data mask (lower 8 bit) signal output to the SD-RAM
148
UDQM
O
Data mask (upper 8 bit) signal output to the SD-RAM
149 to 158
MD0 to MD9
I/O
Two-way data bus with the SD-RAM
159
VDC8
-
Power supply terminal (+1.8V) (for core)
160
VSC8
-
Ground terminal (for core)
161 to 166 MD10 to MD15
I/O
Two-way data bus with the SD-RAM
167
VDIO5
-
Power supply terminal (+3.3V) (for I/O)
168
VSIO5
-
Ground terminal (for I/O)
169 to 176
ADIO0 to ADIO7
I/O
A/D converter input/output terminal (for RF) No used
177
VDC9
-
Power supply terminal (+1.8V) (for core)
178
VSC9
-
Ground terminal (for core)
179
RFD
O
Binary RF signal output terminal No used
180
TESTI
I
Test terminal
181
PDAVDD
-
Power supply terminal (+3.3V) (analog system for PLL-D/A)
182
PDAVSS
-
Ground terminal (analog system for PLL-D/A)
183
PDAREF
O
Reference current output terminal (analog system for PLL-D/A)
184
PDAOUT
O
PLL-D/A output terminal
185
VCTL
I
VCO control voltage input terminal (for PLL)
186
PLLVDD
-
Power supply terminal (+3.3V) (analog system for PLL)
187
PLLVSS
-
Ground terminal (analog system for PLL)
188
RADVRT
I
Reference voltage (top side) input terminal (for RF A/D)
189
RADVDD
-
Power supply terminal (+3.3V) (analog system for RF A/D)
190
RFIN
I
RF signal input from the SA-CD/CD RF amplifier
191
RADVSS
-
Ground terminal (analog system for RF A/D)
192
RADVRB
I
Reference voltage (bottom side) input terminal (for RF A/D)
193
RFSWVSO
O
CD/DVD selection terminal (RFIN side)
194
RFSWVSI
I
CD/DVD selection terminal (ground side)
195
RFSWVDO
O
CD/DVD selection terminal (RFIN side)
196
RFSWVDI
I
CD/DVD selection terminal (power supply side)
197
SADVDD
-
Power supply terminal (+3.3V) (analog system for servo A/D)
198
SADVSS
-
Ground terminal (analog system for servo A/D)
199
ADIMNT
O
Not used
200
TEI
I
Tracking error signal input from the SA-CD/CD RF amplifier
201
FEI
I
Focus error signal input from the SA-CD/CD RF amplifier
202
PI
I
Pull-in signal input from the SA-CD/CD RF amplifier
203
SEI
I
Sled error signal input from the motor/coil driver
204
SP_RV
I
Spindle counter electromotive force input from the motor/coil driver
205
TSD-M
O
Thermal shut down signal output terminal Not used
206
VC0
I
Middle point voltage input from the motor/coil driver
40
SCD-XA1200ES
Pin No.
Pin Name
I/O
Description
207
SSIMON0
I
Not used
208
PI_F
I
Pull-in signial input from the SA-CD/CD RF amplifier (for internal Tracking zero crossing signal
generation)
generation)
209
TE_F
I
Tracking error signal input from the SA-CD/CD RF amplifier (for internal Tracking zero crossing
signal generation)
signal generation)
210
VC1
I
Middle point voltage input from the motor/coil driver (for internal Tracking zero crossing signal
generation)
generation)
211
SDAVDD0
-
Power supply terminal (+3.3V) (analog system for servo PWM)
212
SDAVSS0
-
Ground terminal (analog system for servo PWM)
213, 214
TDOP, TDON
O
Tracking coil drive signal output to the motor/coil driver
215, 216
FDOP, FDON
O
Focus coil drive signal output to the motor/coil driver
217
VDC10
-
Power supply terminal (+1.8V) (for core)
218
VSC10
-
Ground terminal (for core)
219, 220 SLDOA, SLDOB
O
Sled motor drive signal output to the motor/coil driver
221, 222
SPDOA, SPDOB
O
Spindle motor drive signal output to the motor/coil driver
223
SDAVDD1
-
Power supply terminal (+3.3V) (analog system for servo PWM)
224
SDAVSS1
-
Ground terminal (analog system for servo PWM)
225
LOAD
O
Not used
226
JIT
O
Jitter value output to the master controller
227
VDC11
-
Power supply terminal (+1.8V) (for core)
228
VSC11
-
Ground terminal (for core)
229
DFCTI
I
Defect signal input from the SA-CD/CD RF amplifier
230
TZC
I
Tracking zero crossing signal input from the SA-CD/CD RF amplifier
231
MIRR
I
Mirror signal input from the SA-CD/CD RF amplifier
232
VDIO6
-
Power supply terminal (+3.3V) (for I/O)
233
VSIO6
-
Ground terminal (for I/O)
234
INLIM
I
Limit in detection switch input terminal
235
FGMODE
O
Spindle motor break signal output to the motor/coil driver
236
SSIMON1
I
Monitor signal input from the SA-CD/CD RF amplifier
237 to 241
GIO3 to GIO7
I/O
No used
242
VDC12
-
Power supply terminal (+1.8V) (for core)
243
VSC12
-
Ground terminal (for core)
244
SCS
O
Chip select signal output to the SA-CD/CD RF amplifier
245
SSI
I
Serial data input from the SA-CD/CD RF amplifier
246
SSO
O
Serial data output to the SA-CD/CD RF amplifier
247
SCK
O
Serial data transfer clock signal output to the SA-CD/CD RF amplifier
248
VDIO7
-
Power supply terminal (+3.3V) (for I/O)
249
VSIO7
-
Ground terminal (for I/O)
250 to 253 GIO12 to GIO15
I/O
No used
254
FG
I
Motor rotation speed detection signal input terminal Not used
255
M_ON
O
Motor on monitor terminal (for spindle control) Not used
256
LOCK
O
Lock monitor terminal (for spindle control) Not used
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