Sony SCD-555ES Service Manual ▷ View online
45
IC301
CXD8762AQ
IC302
CXD9521Q
50
LRCKI
49
BCKI
48
DATAI
47
VSS
46
VSS
45
LVCK01
44
LVCK02
43
INVO
42
INVI
41
128FSO
40 DINIT
39 INAF
38 OVFLAG
37 CKVDD
36 CTLVDD
35 SYNC
34 MODE
33 SCDATA
32 SHIFT
31 LATCH
38 OVFLAG
37 CKVDD
36 CTLVDD
35 SYNC
34 MODE
33 SCDATA
32 SHIFT
31 LATCH
64
CKTL3
63
DFCKSEL
62
NSCKSEL
61
VSS
60
MUTEL
59
MUTER
58
PWMSEL
57
MTPOL
56
DRPOL
55
VDD
54
DATAVDD
53
SDATAL
52
SDATAR
51
SBCKI
1
NSDOL4
2
AVSSL1
3
NSDOL3
4
AVDDL1
5
AVDDL2
6
NSDOL2
7
AVSSL2
8
NSDOL1
9
VSUBL2
10
64FSI
11
XVDD
12
XOUT
13
XIN
14
XVSS
15
VSUBX
16
VSUBR2
17
NSDOR1
18
AVSSR2
19
NSDOR2
20
AVDDR2
21
AVDDR1
22
NSDOR3
23
AVSSR1
24
NSDOR4
25 VSUBR1
26 VSS
27 VDD
28 NREGCLR
29 SYSM
30 INIT
65
CKTL2
66
CKTL1
67
CKTL0
68
TEST2
69
TEST1
70
DFIOSEL
71
DFLRCK
72
DFDTL
73
DFDTR
74
DFBCK
80
VSUBL1
79
VSS
78
VDD
77
PLMGAIN1
76
PLMGAIN2
75
DFDTEN
S/P
DIGITAL
FILTER
P/S
LINEAR
INTERPOLATOR
NOISE SHAPER
CLOCK
GEN.
MUTE
/INT
SERIAL
TEST
SERIAL
CONTROL
PWM
SEL
SEL
24
24
4
4
4
4
4
4
4
4
4
4
4 4
17
16
R CH PWM
GENERATOR
R CH D/F
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
2 3 4 5 6 7 8 9
18 19 20 21 22 23 24
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
L CH
PWM BUFFER
MASTER CLOCK
GENERATOR
R CH
PWM BUFFER
10 11 12 13 14 15
L CH PWM
GENERATOR
L CH D/F
CLOCK
GENERATOR
3.3V/
5V/
I/O
5V I/O
5V I/O
3.3V/
5V/
I/O
VSS2
L2 (+)
VSS
NC
L2 (
–
)
VDD
VDD2
VSUB (A) L
NC
XVDD
XOUT
NC
XIN
XVSS
XVSUB
NC
VSUB (A) R
VDD2
VDD
R2 (
–
)
NC
VSS
R2 (+)
VSS2
VSS2
R1 (+)
VSS
NC
R1 (–)
VDD
VDD2
VSUB (C)
VSUB (D)
CTLVSS
FIL1
FIL2
MODE
SYNC
MUTE
CTLVDD
CKOSEL0
CKOSEL1
CKOSEL2
C256FSO
DVDD
NSDTIR4
NSDTIR3
NSDTIR2
NSDTIR1
NC
C512FSO
DVSS
DVSS
NSBCKO
NC
NSDTIL1
NSDTIL2
NSDTIL3
NSDTIL4
DVDD
DLPOL
DRPOL
TEST1
TEST2
NSCKSEL
MCKSEL
CLKVDD
LVCKO2
LVCKO1
LVCKO0
CLKVSS
VSUB (D)
VSUB (C)
VDD2
VDD
L1 (–)
NC
VSS
L1 (+)
VSS2
46
– DISPLAY Board –
IC1002
MSM9201-03GS-K
61
62
40
39
38
59
60
57
58
55
56
53
54
51
52
49
50
47
48
45
46
43
44
41
42
65
63
64
66
68
67
70
71
72
73
74
75
76
77
78
79
80
69
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1 2
COMMAND
DECODER
CONTROL
CIRCUIT
GRID
DRIVER
PORT
DRIVER
TIMING
GENERATOR1
TIMING
GENERATOR2
8BIT
SHIFT
REGISTER
WRITE
ADDRESS
COUNTER
COUNTER
READ
ADDRESS
COUNTER
COUNTER
OSCILLATOR
DUTY
CONTROL
DIGIT
CONTROL
ADDRESS
SELESTOR
ADRAM
24W x 4B
DCRAM
24W x 8B
CGRAM
240W x 35B
CGRAM
16W x 35B
AD
DRIVER
SEGMENT
DRIVER
COM23
COM24
OSC0
VFL1
GND
OSC1
CS
RESET
DA
VDD
P1
P2
P3
P4
VFL2
NC
VDISP2
AD1
AD2
CP
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
AD3
AD4
COM2
COM1
VDISP1
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
COM21
COM22
COM19
COM20
COM17
COM18
COM15
COM16
COM13
COM14
COM11
COM12
COM9
COM10
COM7
COM8
COM5
COM6
COM3
COM4
47
4-25.
IC PIN FUNCTION DESCRIPTION
• MAIN BOARD IC509 CXD3008Q
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, DIGITAL FILTER, D/A CONVERTER)
Pin No.
Pin Name
I/O
Description
1
DVDD0
—
Power supply terminal (+5V) (digital system)
2
XRST
I
Reset signal input from the expander (IC902) “L”: reset
3
MUTE
I
Muting control signal input from the CPU (IC901) “H”: muting
4
DATA
I
Serial data input from the CPU (IC901)
5
XLAT
I
Latch signal input from the CPU (IC901)
6
CLOK
I
Clock signal input from the CPU (IC901)
7
SENS
O
Internal status (SENSE) signal output to the CPU (IC901)
8
SCLK
I
Serial data transfer clock input from the CPU (IC901)
9
ATSK
I
Input pin for anti-shock (fixed at “L”)
10
WFCK
O
Write frame clock signal output to the SACD decoder (IC701)
11
XUGF
O
XUGF signal output terminal Not used (open)
12
XPCK
O
XPCK signal output terminal Not used (open)
13
GFS
O
Guard frame sync signal output to the CPU (IC901)
14
C2PO
O
C2 pointer signal output to the SACD decoder (IC701)
15
SCOR
O
Subcode sync OR signal output to the SACD decoder (IC701) and the CPU (IC901)
16
C4M
O
4.2336 MHz clock signal output terminal Not used (open)
17
WDCK
O
Guard subcode sync OR signal output to the SACD decoder (IC701)
18
DVSS0
—
Ground terminal (digital system)
19
COUT
O
Numbers of track counted signal output to the CPU (IC901)
20
MIRR
O
Mirror signal output to the CPU (IC901)
21
DFCT
O
Defect signal output terminal Not used (pull up)
22
FOK
O
Focus OK signal output to the CPU (IC901)
23
PWMI
I
Not used (fixed at “L”)
24
LOCK
O
GFS is sampled by 460 Hz “H” output when GFS is “H”
25
MDP
O
Spindle motor (M3) servo drive signal output to the SACD decoder (IC701)
26
SSTP
I
Detection signal input from limit switch (S1) The optical pick-up is inner position when “H”
27
FSTO
O
2/3 divider output terminal Not used (open)
28
DVDD1
—
Power supply terminal (+5V) (digital system)
29
SFDR
O
Sled servo drive PWM signal (+) output to the BA5938FP (IC502)
30
SRDR
O
Sled servo drive PWM signal (–) output to the BA5938FP (IC502)
31
TFDR
O
Tracking servo drive PWM signal (+) output to the BA5938FP (IC502)
32
TRDR
O
Tracking servo drive PWM signal (–) output to the BA5938FP (IC502)
33
FFDR
O
Focus servo drive PWM signal (+) output to the BA5938FP (IC502)
34
FRDR
O
Focus servo drive PWM signal (–) output to the BA5938FP (IC502)
35
DVSS1
—
Ground terminal (digital system)
36
TEST
I
Input terminal for the test (fixed at “L”)
37
TES1
I
Input terminal for the test (fixed at “L”)
38
VC
I
Middle point voltage (+1.65V) input from the NJM3403AV (IC009)
39
FE
I
Focus error signal input from the CXD1881R (IC001)
40
SE
I
Sled error signal input from the CXD1881R (IC001)
41
TE
I
Tracking error signal input from the CXD1881R (IC001)
42
CE
I
Chip enable signal input from the CXD1881R (IC001)
43
RFDC
I
RF signal (DC level) input from the CXD1881R (IC001)
44
ADIO
O
Output terminal for the A/D converter Not used (open)
48
Pin No.
Pin Name
I/O
Description
45
AVSS0
—
Ground terminal (analog system)
46
IGEN
I
Stabilized current input for operational amplifiers
47
AVDD0
—
Power supply terminal (+5V) (analog system)
48
ASYO
O
Playback EFM full-swing output terminal
49
ASYI
I
Playback EFM asymmetry comparator voltage input terminal
50
RFAC
I
EFM RF signal (AC level) input from the CXD1881R (IC001)
51
AVSS1
—
Ground terminal (analog system)
52
CLTV
I
Internal VCO control voltage input of the EFM playback master PLL
53
FILO
O
Filter output for master clock of the playback EFM master PLL
54
FILI
I
Filter input for master clock of the playback EFM master PLL
55
PCO
O
Phase comparison output for master clock of the playback EFM master PLL
56
AVDD1
—
Power supply terminal (+5V) (analog system)
57
BIAS
I
Playback EFM asymmetry circuit constant current input terminal
58
VCTL
I
Control voltage input terminal for the variable pitch Not used (fixed at “L”)
59
V16M
O
16.9344 MHz clock signal output Not used (open)
60
VPCO
O
PLL charge pump output terminal for the variable pitch Not used (fixed at “L”)
61
DVDD2
—
Power supply terminal (+5V) (digital system)
62
ASYE
I
Playback EFM asymmetry circuit on/off selection signal input terminal
Not used (fixed at “H”)
Not used (fixed at “H”)
63
MD2
I
Digital out on/off control signal input from the CPU (IC901)
“L”: digital out on, “H”: digital out off
“L”: digital out on, “H”: digital out off
64
DOUT
O
Digital audio signal output to the DIGITAL (CD) OUT OPTICAL (IC392)
65
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the digital filter (IC301) and SACD decoder
(IC701)
(IC701)
66
PCMD
O
Serial data output to the digital filter (IC301) and SACD decoder (IC701)
67
BCLK
O
Bit clock signal (2.8224 MHz) output to the digital filter (IC301) and SACD decoder (IC701)
68
EMPH
O
Playback disc output terminal in emphasis mode Not used (open)
69
XTSL
I
Input terminal for the system clock frequency setting Fixed at “H” in this set
70
DVSS2
—
Ground terminal (digital system)
71
XTAI
I
System clock input terminal (33.86688 MHz)
72
XTAO
O
System clock output terminal (33.86688 MHz) Not used (open)
73
SOUT
O
Not used (open)
74
SOCK
O
Not used (open)
75
XOLT
I
Not used (open)
76
SQSO
O
Subcode Q data output to the CPU (IC901)
77
SQCK
I
Subcode Q data reading clock signal input from the CPU (IC901)
78
SCOR
O
Not used (open)
79
SBSO
O
Subcode serial data output to the SACD decoder (IC701)
80
EXCK
I
Subcode serial data reading clock signal input to the SACD decoder (IC701)
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