Sony SA-WFS3 / SS-FS3 Service Manual ▷ View online
SA-WFS3/SS-FS3
49
Pin No.
Pin Name
I/O
Description
78
IOGND
-
Ground terminal
79
MCLK
O
Master clock signal output to the DSP and HDMI transmitter
80
CGND
-
Ground terminal
81
CVCC18
-
Power supply terminal (+1.8V)
82
AUDPVCC18
-
Power supply terminal (+1.8V)
83
AUDPGND
-
Ground terminal
84
XTALOUT
O
System clock output terminal (28.322 MHz)
85
XTALIN
I
System clock input terminal (28.322 MHz)
86
XTALVCC
-
Power supply terminal (+3.3V)
87
REGVCC
-
Power supply terminal (+3.3V)
88
RSVDL
-
Not used
89
RESET
I
Reset signal input from the HDMI controller “L”: reset
90
SCDT
-
Not used
91
INT
O
Interrupt signal output to the HDMI controller
92 to 96
QE23 to QE19
O
Digital video signal output to the HDMI transmitter
97
IOGND
-
Ground terminal
98
IOVCC
-
Power supply terminal (+3.3V)
99 to 105
QE18 to QE12
O
Digital video signal output to the HDMI transmitter
106
IOGND
-
Ground terminal
107
IOVCC
-
Power supply terminal (+3.3V)
108 to 111
QE11 to QE8
O
Digital video signal output to the HDMI transmitter
112
CVCC18
-
Power supply terminal (+1.8V)
113
CGND
-
Ground terminal
114 to 117
QE7 to QE4
O
Digital video signal output to the HDMI transmitter
118
IOGND
-
Ground terminal
119
ODCK
O
Output data clock signal output to the HDMI transmitter
120
IOVCC
-
Power supply terminal (+3.3V)
121 to 124
QE3 to QE0
O
Digital video signal output to the HDMI transmitter
125
CVCC18
-
Power supply terminal (+1.8V)
126
CGND
-
Ground terminal
127
DE
O
Data enable signal output to the HDMI transmitter
128
HSYNC
O
Horizontal sync signal output to the HDMI transmitter
SA-WFS3/SS-FS3
50
HDMI BOARD IC3519 R5F3640DDFBR-128 (HDMI CONTROLLER)
Pin No.
Pin Name
I/O
Description
1 to 5
NC
-
Not used
6
BYTE
I
External data bus width selection signal input terminal Fixed at “L” in this set
7
CNVSS
I
Processor mode selection signal input terminal
8, 9
NC
-
Not used
10
RESET
I
Reset signal input from the system controller “L”: reset
11
XOUT
O
System clock output terminal (10 MHz)
12
VSS
-
Ground terminal
13
XIN
I
System clock input terminal (10 MHz)
14
VCC_3.3V
-
Power supply terminal (+3.3V)
15
NMI
I
Non-maskable interrupt signal input terminal Not used
16 to 18
NC
-
Not used
19
RX_RST
O
Reset signal output to the HDMI receiver “L”: reset
20
RX_INT
I
Interrupt signal input from the HDMI receiver
21
RX_HPD1
O
Hot plug detection control signal output to the HDMI input selector
22 to 26
NC
-
Not used
27
CSCL
O
I2C clock signal output to the EEPROM, HDMI receiver and HDMI transmitter
28
CSDA
I/O
Two-way I2C data bus with the EEPROM, HDMI receiver and HDMI transmitter
29
232COUT
O
Serial data output terminal for RS-232C
30
232CIN
I
Serial data input terminal for RS-232C
31
CLK1
-
Not used
32
NC
-
Not used
33
TX
O
Serial data output to the system controller
34
RX
I
Serial data input from the system controller
35
EEPROMSEL1
O
Write protect signal output to the EEPROM
36 to 39
NC
-
Not used
40
SPDIF_SEL
O
S/PDIF selection signal output terminal Not used
41
TX_5VPWR
O
Power supply on/off control signal output terminal for HDMI +5V power “H”: power on
42
TX_RST
I
Reset signal input from the HDMI transmitter “L”: reset
43
TX_INT
O
Interrupt signal output to the HDMI transmitter
44 to 48
NC
-
Not used
49
eHDMI _IN
-
Not used
50
eHDMI _OUT
-
Not used
51 to 53
TMDS_S1 to TMDS_S3
O
HDMI input selection signal output to the HDMI input selector
54
TMDS_OEB
O
Output enable signal output to the HDMI input selector
55, 56
P5V_SELA, P5V_SELB
O
HDMI +5V power input selection signal output terminal
57 to 59
NC
-
Not used
60
VCC_3.3V
-
Power supply terminal (+3.3V)
61
NC
-
Not used
62
VSS
-
Ground terminal
63, 64
NC
-
Not used
65
MUTE
O
Audio muting control signal output to the system controller
66 to 90
NC
-
Not used
91 to 93
MODEL_SW3 to
MODEL_SW1
I
Model setting terminal
94
AVSS
-
Ground terminal
95
NC
-
Not used
96
VREF
I
Reference voltage (+3.3V) input terminal
97
AVCC
-
Power supply terminal (+3.3V)
98 to 100
NC
-
Not used
SA-WFS3/SS-FS3
51
MAIN BOARD IC4 ADSST-AVR-1115 (DSP)
Pin No.
Pin Name
I/O
Description
1
VDDINT
-
Power supply terminal (+1.2V) (for core)
2
CLKCFG0
I
Core instruction rate to CLKIN (pin 142) ratio selection signal input terminal
Fixed at “L” in this set
Fixed at “L” in this set
3
CLKCFG1
I
Core instruction rate to CLKIN (pin 142) ratio selection signal input terminal
Fixed at “H” in this set
Fixed at “H” in this set
4, 5
BOOTCFG0,
BOOTCFG1
I
Boot mode selection signal input terminal Fixed at “H” in this set
6
GND
-
Ground terminal
7
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
8
GND
-
Ground terminal
9
VDDINT
-
Power supply terminal (+1.2V) (for core)
10
GND
-
Ground terminal
11
VDDINT
-
Power supply terminal (+1.2V) (for core)
12
GND
-
Ground terminal
13
VDDINT
-
Power supply terminal (+1.2V) (for core)
14
GND
-
Ground terminal
15
INT_REQ
O
Interrupt request signal output to the system controller
16
DIR_ERR
I
Error signal input from the digital audio interface receiver
17
AD7
I/O
Two-way address and data bus terminal Not used
18
GND
-
Ground terminal
19
VDDINT
-
Power supply terminal (+1.2V) (for core)
20
GND
-
Ground terminal
21
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
22
GND
-
Ground terminal
23
VDDINT
-
Power supply terminal (+1.2V) (for core)
24 to 26
AD6 to AD4
I/O
Two-way address and data bus terminal Not used
27
VDDINT
-
Power supply terminal (+1.2V) (for core)
28
GND
-
Ground terminal
29, 30
AD3, AD2
I/O
Two-way address and data bus terminal Not used
31
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
32
GND
-
Ground terminal
33, 34
AD1, AD0
I/O
Two-way address and data bus terminal Not used
35
WR*
O
Write enable signal output terminal Not used
36, 37
VDDINT
-
Power supply terminal (+1.2V) (for core)
38
GND
-
Ground terminal
39
RD*
O
Read enable signal output terminal Not used
40
ALE
O
Address latch enable signal output terminal Not used
41 to 43
AD15 to AD13
I/O
Two-way address and data bus terminal Not used
44
GND
-
Ground terminal
45
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
46
AD12
I/O
Two-way address and data bus terminal Not used
47
VDDINT
-
Power supply terminal (+1.2V) (for core)
48
GND
-
Ground terminal
49 to 52
AD11 to AD8
I/O
Two-way address and data bus terminal Not used
53
A16
-
Not used
54
VDDINT
-
Power supply terminal (+1.2V) (for core)
55
GND
-
Ground terminal
56, 57
A17, A18
-
Not used
58
GND
-
Ground terminal
59
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
60
VDDINT
-
Power supply terminal (+1.2V) (for core)
61
GND
-
Ground terminal
62
PF_CE
-
Not used
63
SPI_MAS
-
Not used
64
DPSOA
O
Audio signal output to the stream processor and S-AIR connector
65
DPSOB
O
Audio signal output to the S-AIR connector
66
VDDINT
-
Power supply terminal (+1.2V) (for core)
67
GND
-
Ground terminal
68
VDDINT
-
Power supply terminal (+1.2V) (for core)
SA-WFS3/SS-FS3
52
Pin No.
Pin Name
I/O
Description
69
GND
-
Ground terminal
70
DPSOC
O
Audio signal output to the stream processor
71
DPSOD
O
Audio signal output terminal Not used
72
VDDINT
-
Power supply terminal (+1.2V) (for core)
73
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
74
GND
-
Ground terminal
75
VDDINT
-
Power supply terminal (+1.2V) (for core)
76
GND
-
Ground terminal
77
DPSOE
O
Audio signal output to the S-AIR connector
78
DPSIA
I
Audio signal input from the digital audio interface receiver
79
DPSIB
I
Audio signal input from the HDMI receiver, digital media port connector, AUDIO IN jack and
tuner (FM/AM)
tuner (FM/AM)
80 to 82
DPSIC to DPSIE
I
Audio signal input from the HDMI receiver
83
VDDINT
-
Power supply terminal (+1.2V) (for core)
84, 85
GND
-
Ground terminal
86
DPDVLRCK
O
L/R sampling clock signal output to the stream processor and S-AIR connector
87
DPDVBCK
O
Bit clock signal output to the stream processor and S-AIR connector
88
DPLRCK
I
L/R sampling clock signal input from the digital audio interface receiver and HDMI receiver
89
DPBCK
I
Bit clock signal input from the digital audio interface receiver and HDMI receiver
90
VDDINT
-
Power supply terminal (+1.2V) (for core)
91, 92
GND
-
Ground terminal
93
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
94
DPFSCK
I
Master clock signal input from the digital audio interface receiver and HDMI receiver
95
GND
-
Ground terminal
96
VDDINT
-
Power supply terminal (+1.2V) (for core)
97
NONAUDIO*
I
Audio data input from the digital audio interface receiver
98
SF_CE*
-
Not used
99
VDDINT
-
Power supply terminal (+1.2V) (for core)
100
GND
-
Ground terminal
101
VDDINT
-
Power supply terminal (+1.2V) (for core)
102
GND
-
Ground terminal
103
VDDINT
-
Power supply terminal (+1.2V) (for core)
104
GND
-
Ground terminal
105
VDDINT
-
Power supply terminal (+1.2V) (for core)
106
GND
-
Ground terminal
107, 108
VDDINT
-
Power supply terminal (+1.2V) (for core)
109
GND
-
Ground terminal
110
VDDINT
-
Power supply terminal (+1.2V) (for core)
111
GND
-
Ground terminal
112
VDDINT
-
Power supply terminal (+1.2V) (for core)
113
GND
-
Ground terminal
114
VDDINT
-
Power supply terminal (+1.2V) (for core)
115
GND
-
Ground terminal
116
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
117
GND
-
Ground terminal
118
VDDINT
-
Power supply terminal (+1.2V) (for core)
119
GND
-
Ground terminal
120
VDDINT
-
Power supply terminal (+1.2V) (for core)
121
RESET*
I
Reset signal input from the system controller “L”: reset
122
SPIDS*
I
Device selection signal input from the system controller
123
GND
-
Ground terminal
124
VDDINT
-
Power supply terminal (+1.2V) (for core)
125
SPICLK
I
Serial data transfer clock signal input from the system controller
126
MISO
O
Serial data output to the system controller
127
MOSI
I
Serial data input from the system controller
128
GND
-
Ground terminal
129
VDDINT
-
Power supply terminal (+1.2V) (for core)
130
VDDEXT
-
Power supply terminal (+3.3V) (for I/O)
131
AVDD
-
Power supply terminal (+1.2V) (analog system)
132
AVSS
-
Ground terminal (analog system)
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