DOWNLOAD Sony PHA-1A / PHA-1AEU Service Manual ↓ Size: 1.33 MB | Pages: 31 in PDF or view online for FREE

Model
PHA-1A PHA-1AEU
Pages
31
Size
1.33 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
pha-1a-pha-1aeu.pdf
Date
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PHA-1A/1AEU
17
IC509  TPS2553DBVR
IC511  74LVC1G175GW-125
IC704  BD6047AGUL-E2
GND 2
EN 3
IN 1
4 FAULT
5 ILLM
6 OUT
CHARGE
PUMP
UNDERVOLTAGE
LOCKOUT
THERMAL
SENSE
CURRENT
LIMIT
4-ms
DEGLITCH
8-ms
DEGLITCH
CURRENT
SENSE
DRIVER
+
–
RREVERSE VOLTAGE
COMPARATOR
D
CP
MR
D 3
GND
CP
2
1
6
VCC
5
MR
4
Q
Q
6
A1
IN
IN
IN
A2
A3
B1
IN
IN
GND
B2 B3
OUT
OUT
C1
FLGB
C3
TIMING
GENERATOR
UVLO
VREF
OVLO
OCP
TSD
OSC
INITIAL
DELAY
NVP
GATE
DRIVER
INITIAL
DELAY
C2
PHA-1A/1AEU
18
•  IC Pin Function Description
MAIN  BOARD  IC401  LC87F17C8AUWA-2H (USB  CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
SERIAL-SW
I
Serial No. write mode switch input terminal    “H”: serial No. write mode
2
/RES
I
Reset signal input terminal    “L”: reset
3
XT1
I
System clock input terminal    Not used
4
NC
O
Not used
5
VSS1
-
Ground terminal
6
CF1
I
System clock input terminal (12 MHz)
7
CF2
O
System clock output terminal (12 MHz)
8
VDD1
-
Power supply terminal (+3.3V)
9 to 11
OPT_1 to OPT_3
I
Hardware option input terminal    Not used
12
CP_SCL
O
Serial data transfer clock signal output to the MFI
13
CP_SDA
I/O
Two-way serial data bus with the MFI
14
—
I
Not used
15
VBUS_SW
I
VBUS current selection signal input terminal    Fixed at “L” in this unit
16
AUX_SW
I
AUX selection signal input terminal
17
MCLK_IN
I
Digital audio master clock signal input from the USB audio processor
18
MCLK_OUT
O
Digital audio master clock signal output to the D/A converter
19
VDD2
-
Power supply terminal (+3.3V)
20
VSS2
-
Ground terminal
21
CP_RST
O
Reset signal output to the MFI    “L”: reset
22
NC
O
Not used
23
SDAT_IN_AUX
I
Digital audio data input from the USB audio processor
24
BCLK_IN_AUX
I
Digital audio bit clock signal input from the USB audio processor
25
LRCK_IN_AUX
I
Digital audio L/R sampling clock signal input from the USB audio processor
26
SDAT_OUT
O
Digital audio data output to the D/A converter
27
BCLK_OUT
O
Digital audio bit clock signal output to the D/A converter
28
LRCK_OUT
O
Digital audio L/R sampling clock signal output to the D/A converter
29 to 33
OPT_4 to OPT_8
I
Hardware option input terminal    Not used
34
SDAT_IN
I
Digital audio data input terminal    Not used
35
BCLK_IN
I
Digital audio bit clock signal input terminal    Not used
36
LRCK_IN
I
Digital audio L/R sampling clock signal input terminal    Not used
37
UHD–
I/O
Two-way USB data (–) bus with the INPUT (for iPhone/iPad/iPod) connector
38
UHD+
I/O
Two-way USB data (+) bus with the INPUT (for iPhone/iPad/iPod) connector
39
VDD3
-
Power supply terminal (+3.3V)
40
VSS3
-
Ground terminal
41
UFILT
-
USB interface PLL fi lter terminal
42
AFILT
-
Audio PLL fi lter terminal
43
MUTE 1
O
Audio (L-ch) muting on/off control signal output terminal    “L”: muting on
44
MUTE 2
O
Audio (R-ch) muting on/off control signal output terminal    “L”: muting on
45
LED1
O
LED drive signal output terminal for the POWER/CHG indicator (green color)    “H”: LED on
46
BATT_CK
I
Battery level check terminal
47
NC
O
Not used
48
VBUS-OFF
O
VBUS on/off control signal output terminal for the INPUT (for iPhone/iPad/iPod) connector    
“L”: VBUS on
PHA-1A/1AEU
19
Pin No.
Pin Name
I/O
Description
1
XSC0
O
System clock output terminal (12 MHz)
2
VCCHSRT
-
Power supply terminal (+3.3V) (analog system)
3
GNDHSRT
-
Ground terminal (analog system)
4
RREF
I
External reference resistor connection terminal
5
USBDM
I/O
Two-way USB data (–) bus with the INPUT (for PC/WALKMAN/Xperia) connector
6
USBDP
I/O
Two-way USB data (+) bus with the INPUT (for PC/WALKMAN/Xperia) connector
7
VCCA_U20
-
Power supply terminal (+3.3V) (analog system)
8
GNDA_U20
-
Ground terminal (analog system)
9
VCC3V
-
Power supply terminal (+3.3V) (digital system)
10
VCC
O
External fi lter capacitor connection terminal
11
GND
-
Ground terminal (digital system)
12 to 17
XGPI_0 to XGPI_5
I/O
Not used
18
GND
-
Ground terminal (digital system)
19
XPWDN
O
Power down control signal output terminal    Not used
20, 21
XD6, XD7
I
System clock input terminal    Not used
22
XD0
I
Serial data input terminal    Not used
23
XD1
O
Serial data output terminal    Not used
24
XHDA_BCLK
O
Bit clock signal output terminal    Not used
25
XHDA_SDI
I
Serial data input terminal    Not used
26
XHDA_SYNC
O
Frame sync signal output terminal    Not used
27
XHDA_RST
O
Reset signal output terminal    Not used
28
XHDA_SDO
O
Serial data output terminal    Not used
29
VCC3V
-
Power supply terminal (+3.3V) (digital system)
30
XMADC_SDIN0
I
I2S serial data input terminal    Not used
31
XMADC_SCLK
I/O
I2S bit clock signal input/output terminal    Not used
32
XMADC_MCLK
O
I2S master clock signal output terminal    Not used
33
XMADC_LRCK
I/O
I2S L/R sampling clock signal input/output terminal    Not used
34
X2ADC_SDIN0
I
I2S serial data input terminal    Not used
35
X2ADC_SCLK
I/O
I2S bit clock signal input/output terminal    Not used
36
X2ADC_LRCK
I/O
I2S L/R sampling clock signal input/output terminal    Not used
37
X2ADC_MCLK
O
I2S master clock signal output terminal    Not used
38
XSPDIFO_0
O
S/PDIF signal output terminal    Not used
39
GND
-
Ground terminal (digital system)
40
XSPDIFI_0
I
S/PDIF signal input terminal    Not used
41 to 48
XPEE_D0 to 
XPEE_D7
I/O
Two-way serial data bus with the fl ash memory
49 to 52
XGPIO_8 to 
XGPIO_11
I/O
Not used
53
VCC3V
-
Power supply terminal (+3.3V) (digital system)
54
XGPIO_7
O
AUX selection signal output terminal
55
XRSTO
O
Reset signal output terminal    Not used
56
XSSDA
I/O
Two-way slave serial data bus terminal    Not used
57
XSSCL
I/O
Two-way slave serial clock bus terminal    Not used
58 to 60
XGPIO_12 to 
XGPIO_14
I/O
Not used
61
GND
-
Ground terminal (digital system)
62
XGPIO_15
I/O
Not used
63
XMSDA
I/O
Two-way master serial data bus terminal    Not used
64
XMSCL
I/O
Two-way master serial clock bus terminal    Not used
65 to 72
XPEE_A0 to 
XPEE_A7
O
Address signal output to the fl ash memory
73
VCC3V
-
Power supply terminal (+3.3V) (digital system)
74 to 81
XPEE_A8 to 
XPEE_A15
O
Address signal output to the fl ash memory
82
XPEE_CEN
O
Chip enable signal output to the fl ash memory
83
XPEE_WRN
O
Write enable signal output to the fl ash memory
84
XPEE_RDN
O
Read enable signal output to the fl ash memory
85
X2DAC_MCLK
O
I2S master clock signal output terminal    Not used
86
X2DAC_LRCK
I/O
I2S L/R sampling clock signal input/output terminal    Not used
MAIN  BOARD  IC601  CM6631A (USB  AUDIO  PROCESSOR)
PHA-1A/1AEU
20
Pin No.
Pin Name
I/O
Description
87
X2DAC_SCLK
I/O
I2S bit clock signal input/output terminal    Not used
88
X2DAC_SDOUT
O
I2S serial data output terminal    Not used
89
XMDAC_SDOUT0
O
Digital audio data output to the USB controller
90 to 92
NC
-
Not used
93
XMDAC_SCLK
O
Digital audio bit clock signal output to the USB controller
94
XMDAC_LRCK
O
Digital audio L/R sampling clock signal output to the USB controller
95
XMDAC_MCLK
O
Digital audio master clock signal output to the USB controller
96
XSEL_PWR
I
Power selection signal input terminal    “L”: bus power, “H”: self power    Fixed at “H” in this unit
97
VCC3V
-
Power supply terminal (+3.3V) (digital system)
98
XRST
I
Reset signal input terminal    Not used
99
XTEST
I
Test mode selection signal input terminal    “L”: normal operation, “H”: test mode    
Fixed at “L” in this unit
100
XSCI
I
System clock input terminal (12 MHz)
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