Sony NW-HD1 Service Manual ▷ View online
37
NW-HD1
Pin No.
Pin Name
I/O
Description
169
MSINS
I
Card detection signal input from the memory stick interface Not used
170
P17
I
HOLD key detection signal input terminal “L”: hold
171
P10/DADT
O
Audio data input from the memory stick interface Not used
172
P11/ADDT
I
Audio data input from the sub system controller
173
P12/LRCK
I
L/R sampling clock signal input from the sub system controller
174
P13/BCK
I
Bit clock signal input from the sub system controller
175
P14/FS256
O
Clock signal (11.2896 MHz) output to the multi interface
176
P15/MUTFGL
O
Not used
177
P15/MUTFGR
O
Not used
178
DVDD3
—
Power supply terminal (+1.2V) (for core)
179
DVSS5
—
Ground terminal
180
VDIO5
—
Power supply terminal (+1.8V) (for I/O interface)
181
PJ0/WAIT
I
Wait signal input from the multi interface
182
PJ1/RE
O
Read signal output to the multi interface
183
PJ2/LWR/LB
O
Write strobe signal output to the multi interface (lower byte)
184
PJ3/UWR/UB
O
Write strobe signal output to the multi interface (upper byte)
185
PJ4/WE
O
Write signal output to the multi interface
186
PK0/CS0
O
Chip select signal output to the multi interface
187
PK1/CS1
O
Chip select signal output terminal Not used
188
PK2/XBOOT
I
Boot mode selection signal input terminal Not used
189
PK3/MS_SIO
I
Boot mode selection signal input terminal Not used
190
PK4
I
Not used
191
PK5/CS5
I
Chip select signal input from the multi interface
192
PK6/CS6
I
Chip select signal input from the multi interface
193
PK7/CS7
I
Chip select signal input from the multi interface
194
DVSS6
—
Ground terminal
195
VDIO6
—
Power supply terminal (+1.8V) (for I/O interface)
196 to 207
PL0/A0 to PL7/A7,
PM0/A8 to PM3/A11
O
Address signal output to the flash memry and mullet interface
208
DVSS6
—
Ground terminal
38
NW-HD1
MAIN BOARD IC2001 1S1R72003BOOA100 (USB CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
R1
I/O
Internal operation setting terminal
2
N.C.
—
Not used
3
AVSS
—
Ground terminal (analog system)
4
AVDD
—
Power supply terminal (+3.3V) (analog system)
5
AVSS
—
Ground terminal (analog system)
6
AVDD
—
Power supply terminal (+3.3V) (analog system)
7
AVSS
—
Ground terminal (analog system)
8
DP
I/O
USB data (+) input/output terminal
9
AVSS
—
Ground terminal (analog system)
10
DM
I/O
USB data (–) input/output terminal
11
AVSS
—
Ground terminal (analog system)
12
AVDD
—
Power supply terminal (+3.3V) (analog system)
13
TSTEN
I
Input terminal for the test mode setting
14
VBUS
I
USB bus detection signal input terminal
15
XRESET
I
Reset signal input from the multi interface
16
XSLEEP
I
Sleep signal input from the multi interface
17 to 24
CA0 to CA7
I
Address signal input from the multi interface
25
VSS
—
Ground terminal (logic system)
26
VDD
—
Power supply terminal (+3.3V) (logic system)
27
XCS
I
Chip select signal input from the multi interface
28
XRD
I
Read signal input from the multi interface
29
XWAIT
O
Wait signal output to the multi interface
30
XWR
I
Write signal input from the multi interface
31
XINT
O
Interrupt request signal output to the multi interface
32 to 35
CD0 to CD3
I/O
Two-way data bus with the multi interface and liquid crystal display unit
36
VSS
—
Ground terminal (logic system)
37 to 40
CD4 to CD7
I/O
Two-way data bus with the multi interface and liquid crystal display unit
41
VDD
—
Power supply terminal (+3.3V) (logic system)
42
ATPGEN
I
Input terminal for the test mode setting
43
SCANEN
I
Input terminal for the test mode setting
44, 45
TPORT0, TPORT1
I/O
Input/output terminal for the test mode setting
46, 47
TIN0, TIN1
I
Input terminal for the test mode setting
48
VSS
—
Ground terminal (logic system)
49
OSCOUT
O
Clock signal output terminal Not used
50
VSS
—
Ground terminal (logic system)
51
VDD
—
Power supply terminal (+3.3V) (logic system)
52
XHRESET
I
Reset signal input terminal Not used
53 to 60 HDD4 to HDD11
I/O
Two-way data bus with the multi interface and hard disk drive unit
61
VSS
—
Ground terminal (logic system)
62 to 69
HDD0 to HDD3,
HDD12 to HDD15
I/O
Two-way data bus with the multi interface and hard disk drive unit
70
VDD
—
Power supply terminal (+3.3V) (logic system)
71
HDMARQ
I
DMA request signal input from the hard disk drive unit
72
XHIOW
O
Write signal output to the hard disk drive unit
73
XHIOR
O
Read signal output to the hard disk drive unit
39
NW-HD1
Pin No.
Pin Name
I/O
Description
74
HIORDY
I
Wait signal input from the hard disk drive unit
75
VSS
—
Ground terminal (logic system)
76
VDD
—
Power supply terminal (+3.3V) (logic system)
77
XHDMACK
O
DMA acknowledge signal output to the hard disk drive unit
78
HINTRQ
I
Interrupt request signal input from the hard disk drive unit
79
HA1
O
Address signal output to the multi interface and hard disk drive unit
80
XHPDIAG
I
Diagnosis sequence compression signal input from the hard disk drive unit
81, 82
HA0, HA2
O
Address signal output to the multi interface and hard disk drive unit
83, 84
HCS0, HCS1
O
Chip select signal output to the hard disk drive unit
85
XHDASP
I
Drive valid signal and slave drive detection signal input from the hard disk drive unit
86
VSS
—
Ground terminal (logic system)
87, 88
CLKSEL0,
CLKSEL1
I
Input terminal for oscillation frequency setting Fixed at 12 MHz in this set
89
VSS
—
Ground terminal (logic system)
90
XVSS
—
Ground terminal (logic system)
91
XVDD
—
Power supply terminal (+3.3V) (logic system)
92
VDD
—
Power supply terminal (+3.3V) (logic system)
93
PVDD
—
Power supply terminal (+3.3V) (for PLL)
94
VDD
—
Power supply terminal (+3.3V) (logic system)
95
PVSS
—
Ground terminal (for PLL)
96 to 98
NC
—
Not used
99
XI
I
Sub system clock input terminal (12MHz)
100
XO
O
Sub system clock output terminal (12MHz)
40
NW-HD1
MAIN BOARD IC7001 CXD1616GH (MULTI INTERFACE)
Pin No.
Pin Name
I/O
Description
1
XTAL
I
Sub system clock input terminal Not used
2
EXTAL
O
Sub system clock output terminal Not used
3
CLK2550A
O
Clock signal (22.5792 MHz) output to the sub system controller
4
CLK2550X
O
Clock signal (22.5792 MHz) inversion output to the sub system controller
5
XOSCSTP
I
Oscillation stop signal input terminal Not used
6
XRESET
I
Reset signal input from the main system controller
7
EXCLKIN
I
Clock signal (176 kHz) input from the main system controller
8 to 30
A1 to A23
I
Address signal input from the main system controller
31 to 46
D0 to D15
I/O
Two-way data bus with the main system controller and flash memory
47 to 49
XCS1 to XCS3
I
Chip select signal input from the main system controller
50
XRD
I
Read signal input from the main system controller
51
XWR
I
Write signal input from the main system controller
52
XLB
I
Write strobe signal input from the main system controller (lower byte)
53
XUB
I
Write strobe signal input from the main system controller (upper byte)
54
XWAIT
I
Wait signal input from the main system controller
55, 56
NC
—
Not used
57
XINTREQG
O
Interrupt request signal output to the main system controller
58
XINTREQH
O
Interrupt request signal output to the main system controller
59
XINTREQU
O
Interrupt request signal output to the main system controller
60 to 72
SA0 to SA12
O
Address signal output to the SD-RAM
73, 74
BA0, BA1
O
Bank selection address signal output to the SD-RAM
75 to 90
SD0 to SD15
I/O
Two-way data bus with the SD-RAM
91
XSCS
O
Chip select signal output to the SD-RAM
92
XRAS
O
Row address strobe signal output to the SD-RAM
93
XCAS
O
Column address strobe signal output to the SD-RAM
94
XSWE
O
Write enable signal output to the SD-RAM
95
LDQM
O
I/O mask signal output to the SD-RAM (lower byte)
96
UDQM
O
I/O mask signal output to the SD-RAM (upper byte)
97
SDCLK
O
Clock signal output to the SD-RAM
98
SDCKE
O
Clock enable signal output to the SD-RAM
99
UA0
O
Address signal output to the USB controller and liquid crystal display unit
100 to 106
UA1 to UA7
O
Address signal output to the USB controller
107 to 114
UD0 to UD7
I/O
Two-way data bus with the USB controller and liquid crystal display unit
115
XUCS0
O
Chip select signal output to the USB controller
116
XUCS1
O
Chip select signal output to the liquid crystal display unit
117
XURD
O
Read signal output to the USB controller and liquid crystal display unit
118
XUWR
O
Write signal output to the USB controller and liquid crystal display unit
119
XUWAIT
I
Wait signal output to the USB controller
120
XUINTREQ
I
Interrupt request signal output to the USB controller
121 to 123
HA0 to HA2
I
Address signal input from the USB controller
124 to 139
HD0 to HD15
I/O
Two-way data bus with the USB controller and hard disk drive unit
140, 141 XHCS0, XHCS1
O
Chip select signal output to the hard disk drive unit
142
XHIOR
O
Read signal output to the hard disk drive unit
143
XHIOW
O
Write signal output to the hard disk drive unit
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