Sony NW-HD1 Service Manual ▷ View online
33
NW-HD1
IC9501
BQ24010ADRCR
OUT
10
IN 1
BAT
9
VCC
VCC
V (ISET)
VSET
VI (BAT)
VI (BAT)
VI (BAT)
VI (BAT)
VO (REG)
2
TS
8
STAT1 3
PG
7
STAT2 4
ISET
6
VSS 5
CHARGE
CONTROL,
TIMER,
AND
DISPLY
LOGIC
DEGLITCH
VO (REG)
VI (BAT)
V (SLP)
DEGLITCH
VI (SET)
VI (SET)
DEGLITCH
DEGLITCH
VCC
VCC
THERMAL
SHUTDOWN
VO (REG)
REFERENCE
AND BIAS
IC9504
TPS2113PWR
STAT 1
IN1
8
EN
0.8V
1
µ
A
0.5V
2
OUT
7
VSNS 3
IN2
6
5
ILIM 4
GND
CHARGE
PUMP
THERMAL
SENSE
CROSS-CONDUCTION
DETECTOR
IN2
ULVO
IN1
ULVO
VDD
ULVO
INTERNAL
VDD
CONTROL
LOGIC
34
NW-HD1
•
IC Pin Function Description
MAIN BOARD IC1003 CXR704060-201GA (SYSTEM CONTROLLER, D/A CONVERTER)
Pin No.
Pin Name
I/O
Description
1
VDIO0
—
Power supply terminal (+1.8V) (for I/O interface)
2 to 10
PM4/A12 to
PM7/A15,
PN0/A16 to
PN4/A20
O
Address signal output to the flash memory and multi interface
11 to 13
PN5/A21 to
PN7/A23
O
Address signal output to the multi interface
14
DVSS7
—
Ground terminal
15 to 22
FAD0 to FAD7
I/O
Not used
23
FCLE
O
Not used
24
FALE
O
Not used
25
VDIODF
—
Power supply terminal (for NAND flash memory interface) Not used
26
FWE
O
Not used
27
PRE
O
Not used
28
FWP
O
Not used
29
FCE0
O
Not used
30
FRB0
I
Not used
31
FCE1
O
Not used
32
FRB1
I
Not used
33
PP0/RP
O
Wake up signal output to the sub system controller
34
PP1/RB
O
Communication request signal output to the sub system controller
35
DVDD0
—
Power supply terminal (+1.2V) (for core)
36
DVSS1
—
Ground terminal
37
VDIO1
—
Power supply terminal (+1.8V) (for I/O interface)
38 to 53
PO0/D0 to PO7/D7,
PB0/D8 to PB7/D15
I/O
Two-way data bus with the flash memory and multi interface
54
PA0/PWM
O
Not used
55
PA1/SDA
O
Not used
56
PA2/SCL
O
Not used
57
PC0/SCK0
I
Serial clock signal input from the sub system controller
58
PC1/SO0
O
Serial data output to the sub system controller
59
PC2/SI0
I
Serial data input from the sub system controller
60
PC3/SCS0
O
Chip select signal output to the sub system controller
61
DVSS2
—
Ground terminal
62
VDIO2
—
Power supply terminal (+1.8V) (for I/O interface)
63
KDI
O
Not used
64
KRB
O
Not used
65
KCLK
O
Not used
66
KCS
O
Not used
67
KDO
O
Not used
68
TEST4
I
Input terminal for the test mode setting
69
PE0/TXD0
O
Data output terminal Not used
70
PE1/RXD0
I
Data input terminal Not used
71
PE2/TXD1
O
Strobe signal output to the power control
35
NW-HD1
Pin No.
Pin Name
I/O
Description
72
PE3/RXD1
I
Data input terminal Not used
73
PE4/SCK1
O
Serial clock signal output to the power control and real time clock
74
PE5/SO1
O
Serial data output to the power control and real time clock
75
PE6/SI1
I
Serial data input from the real time clock
76
PE7/SCS1
O
Chip enable signal output to the real time clock
77
XOUT/CKO
O
Clock signal (176 kHz) output to the multi interface
78
DVDD1
—
Power supply terminal (+1.2V) (for core)
79
DVSS3
—
Ground terminal
80
VDIO3
—
Power supply terminal (+1.8V) (for I/O interface)
81
PF0/EC0/INT3
I
Interrupt request signal input from the sub system controller
82
PF1/T1
O
Shut down signal output to the DC/DC converter
83
PF2/EC2/INT4
I
Interrupt request signal input from the multi interface
84
PF3/T3
O
Clock signal (176 kHz) output to the power control
85
PF4/BEEP
O
Beep signal output to the headphone amplifier
86
PG0/DACK0
I
Ready/busy selection signal input from the flash memory “L”: busy, “H”: ready
87
PG1/DREQ0/INT5
I
Interrupt request signal input from the sub system controller
88
PG2/DACK1/INT6
I
Interrupt request signal input from the multi interface
89
PG3/DREQ1/INT7
I
Interrupt request signal input from the multi interface
90 to 93
TEST2, TEST3,
TEST0, TEST1
I
Input terminal for the test mode setting
94
TACK
O
Bus response signal output terminal Not used
95
EVA
I
EVA mode selection signal input terminal Not used
96
AVSAD
—
Ground terminal (for A/D converter)
97
AVDAD
—
Power supply terminal (+2.4V) (for A/D converter)
98
AN0
I
Battery voltage monitor input terminal (A/D input)
99
AN1
I
Not used
100
AN2
I
Acceleration detection signal of X shaft direction input from the acceleration sensor
101
AN3
I
Acceleration detection signal of Y shaft direction input from the acceleration sensor
102
AN4
I
Acceleration detection signal of Z shaft direction input from the acceleration sensor
103, 104
AN5, AN6/INT8
I
Set key input terminal (A/D input)
105
AN7/INT9
I
Remote commander key input terminal (A/D input)
106
RST
I
Reset signal input from the power control
107
RAMBK
I
RAM back up control signal input terminal Not used
108
VDBK
—
Power supply terminal (+1.2V) (for RAM back up)
109
TDI
I
Data input terminal (for JTAG) Not used
110
TMS
I
Test mode control signal input terminal (for JTAG) Not used
111
TCK
I
Clock signal input terminal (for JTAG) Not used
112
TRST
I
Reset signal input terminal (for JTAG) Not used
113
TDO
O
Data output terminal (for JTAG) Not used
114
VDIOJT
—
Power supply terminal (+1.8V) (for JTAG)
115
DVDD2
—
Power supply terminal (+1.2V) (for core)
116
DVSS4
—
Ground terminal
117
VDIO4
—
Power supply terminal (+1.8V) (for I/O interface)
118
PD0/CONNECT
O
Test terminal for debug Not used
119
PD1/XVDATA
O
Test terminal for debug Not used
36
NW-HD1
Pin No.
Pin Name
I/O
Description
120
PD2/DPLS
O
Test terminal for debug Not used
121
PD3/DMNS
O
Test terminal for debug Not used
122
PD4/TXDPLS
O
Test terminal for debug Not used
123
PD5/TXDMNS
O
Test terminal for debug Not used
124
PD6/TXENL
O
Test terminal for debug Not used
125
PD7/SUSPEND
O
Test terminal for debug Not used
126
VBUS
I
Not used
127
VDIOUS
—
Power supply terminal (for USB transceiver) Not used
128
UDM
I/O
Not used
129
UDP
I/O
Not used
130
TRON
O
Not used
131
AVSDA
—
Ground terminal (for internal D/A converter)
132
VREFER
O
Reference voltage output terminal (R-ch)
133
AOUTR
O
Analog audio signal output to the headphone amplifier (R-ch)
134
AOUTL
O
Analog audio signal output to the headphone amplifier (L-ch)
135
VREFL
O
Reference voltage output terminal (L-ch)
136
AVDDA
—
Power supply terminal (+2.4V) (for internal D/A converter)
137
XTAL
O
Main system clock output terminal (22.5792 MHz)
138
EXTAL
I
Main system clock input terminal (22.5792 MHz)
139
AVDMO
—
Power supply terminal (+2.4V) (for main system clock oscillator)
140
AVSOSC
—
Ground terminal (for main and sub system clock oscillator)
141
TX
O
Sub system clock output terminal (16 MHz)
142
ETX
I
Sub system clock input terminal (16 MHz)
143
AVDUO
—
Power supply terminal (+2.4V) (for sub system clock oscillator)
144
AVSPLL
—
Ground terminal (for PLL)
145
AVDPLL
—
Power supply terminal (+3.3V) (for PLL analog system)
146
PQ0/PGMTR0
O
Sleep signal output to the power control
147
PQ1/PGMTR1
O
Starting factor clear signal output to the power control
148
PQ2/PGMTR2
I
Charge progress signal input from the charge control
149
PQ3/PGMTR3
I
Charge completion signal input from the charge control
150
PQ4
I
Power good signal input from the power switch
151
PQ5
O
Sleep signal output to the multi interface
152
PQ6
O
Reset signal output to the sub system controller
153
PQ7
O
Reset signal output to the multi interface
154
DVSS8
—
Ground terminal
155
VDIO7
—
Power supply terminal (+1.8V) (for I/O interface)
156
PR0
O
Battery voltage monitor on/off control signal output terminal
157 to 161
PR1 to PR5
—
Not used
162
PR6
O
Headphone/line selection signal output to the headphone amplifier
163
PR7
O
Muting on/off control signal output to the headphone amplifier
164
DVSS9
—
Ground terminal
165
VDIOMS
—
Power supply terminal (+3.3V) (for memory stick interface) Not used
166
MSDIO
I/O
Two-way data bus with the memory stick interface Not used
167
MSBS
O
Bus state signal output to the memory stick interface Not used
168
MSSCLK
O
Clock signal output to the memory stick interface Not used
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