Sony NW-A805 / NW-A806 / NW-A808 / NWZ-A815 / NWZ-A816 / NWZ-A818 Service Manual ▷ View online
33
NW-A805/A806/A808/NWZ-A815/A816/A818
Pin No.
Pin Name
I/O
Description
E19
FLASHCLK
O
Flash clock output to the D flip-flop
E20
AB0_A7
O
Address signal output to the USB controller
E21 to E23
NC
-
Not used
E24
AB0_XDRQ
I
DMA request signal input from the USB controller
E25
AB0_D4
I/O
Serial date input/output with the USB controller
E26
NC
-
Not used
F1
DGND
-
Ground terminal
F2
CHGVBUS
-
Not used
F3, F4
NC
-
Not used
F5
IO_B
-
Not used
F22
AB0_CSZ2
O
Chip select signal output to the USB controller
F23
AB0_XACK
O
DMA acknowledge signal output to the USB controller
F24, F25
AB0_D3, AB0_D5
I/O
Serial date input/output with the USB controller
F26
NC
-
Not used
G1
DVDD
-
Power supply terminal
G2, G3
NC
-
Not used
G4
EXTRST
I
Reset signal input from the reset switch
G5
NC
-
Not used
G22
ETHER_XINT
-
Not used
G23 to
G25
AB0_D15 to
AB0_D13
I/O
Serial date input/output with the USB controller
G26
NC
-
Not used
H1
USBSUSPD
-
Not used
H2
NC
-
Not used
H3 to H5
SDR_DATA25,
SDR_DATA27,
SDR_DATA27,
SDR_DATA31
I/O
Serial data input/output with the 256Mbit SD-RAM
H8
NAND_RBZ1
O
Read/busy signal outoput to the NAND flash memory
H9 to H15
NC
-
Not used
H16
AB0_WRZ
O
Write strobe signal output to the USB controller
H17
NC
-
Not used
H18, H19
AB0_A1, AB0_A2
O
Address signal output to the USB controller
H22 to
H25
AB0_D8, AB0_D9,
AB0_D7, AB0_D6
I/O
Serial date input/output with the USB controller
H26
NC
-
Not used
J1 to J3
IO_A
-
Not used
J4, J5
SDR_DATA29,
SDR_DATA30
I/O
Serial data input/output with the 256Mbit SD-RAM
J8
NAND_RBZ2
O
Read/busy signal outoput to the NAND flash memory
J9, J10
NC
-
Not used
J11 to J17
GND
-
Ground terminal
J18
NC
-
Not used
J19
AB0_RDZ
O
Read strobe signal output to the USB controller
J22 to
J24
AB0_D10 to
AB0_D12
I/O
Serial date input/output with the USB controller
J25
CHGGND1
-
Ground terminal
J26
NC
-
Not used
K1 to K3
VDD_L1
-
Power supply terminal
34
NW-A805/A806/A808/NWZ-A815/A816/A818
Pin No.
Pin Name
I/O
Description
K4, K5
SDR_DATA28,
SDR_DATA26
I/O
Serial data input/output with the 256Mbit SD-RAM
K8
NAND_RBZ3
O
Read/busy signal outoput to the NAND flash memory
K9
NAND_DA6
I/O
Serial date input/output with the NAND flash memory
K10 to
K18
GND
-
Ground terminal
K19
NC
-
Not used
K22
LCD_HSYNC
O
Horizontal sync signal output to the level shift
K23
NC
-
Not used
K24
LCD_VSYNC
O
Vertical sync signal output to the level shift
K25
CHGGND2
-
Ground terminal
K26
NC
-
Not used
L1 to L5,
L8
SDR_DATA23 to
SDR_DATA20,
SDR_DATA24,
SDR_DATA24,
SDR_DATA19
I/O
Serial data input/output with the 256Mbit SD-RAM
L9
NAND_DA4
I/O
Serial date input/output with the NAND flash memory
L10
GND
-
Ground terminal
L11
NC
-
Not used
L17, L18
GND
-
Ground terminal
L19, L22
to L25
LCD_B1 to
LCD_B5
O
Video signal (B) output to the level shift
L26
NC
-
Not used
M1 to M5,
M8
SDR_DATA18 to
SDR_DATA13
I/O
Serial data input/output with the 256Mbit SD-RAM
M9
NAND_CEZ0
O
Chip enable signal output to the NAND flash memory
M10,
M17, M18
GND
-
Ground terminal
M19
LCD_B0
O
Video signal (B) output to the level shift
M22 to
M25
LCD_G0 to
LCD_G3
O
Video signal (G) output to the level shift
M26
NC
-
Not used
N1 to
N5, N8
SDR_DATA12 to
SDR_DATA7
I/O
Serial data input/output with the 256Mbit SD-RAM
N9, N10,
N17 to
N19
GND
-
Ground terminal
N22, N23
LCD_G4, LCD_G5
O
Video signal (G) output to the level shift
N24, N25
LCD_R0, LCD_R1
O
Video signal (R) output to the level shift
N26
VMICIN
I
Power supply voltage input terminal
P1 to P4
SDR_DATA5 to
SDR_DATA2
I/O
Serial data input/output with the 256Mbit SD-RAM
P5
SDR_DQM0
O
Write mask signal output to the 256Mbit SD-RAM
P8
SDR_DATA6
I/O
Serial data input/output with the 256Mbit SD-RAM
P9
GND
-
Ground terminal
P10
RESETZ
O
Reset signal output to the USB controller
P17 to P19
GND
-
Ground terminal
P22
LCD_R3
O
Video signal (R) output to the level shift
35
NW-A805/A806/A808/NWZ-A815/A816/A818
Pin No.
Pin Name
I/O
Description
P23
LCD_PXCLK
O
Clock signal output to the level shift
P24
NC
-
Not used
P25, P26
IO_A
-
Not used
R1
SDR_DATA0
I/O
Serial data input/output with the 256Mbit SD-RAM
R2 to R4
SDR_DQM3 to
SDR_DQM1
O
Write mask signal output to the 256Mbit SD-RAM
R5
SDR_WEZ
O
Write enable signal output to the 256Mbit SD-RAM
R8
SDR_DATA1
I/O
Serial data input/output with the 256Mbit SD-RAM
R9
GND
-
Ground terminal
R10
NC
-
Not used
R17
U70_CTSZ
-
Not used
R18
U70_RTSZ
-
Not used
R19
GND
-
Ground terminal
R22, R23
LCD_R2, LCD_R4
O
Video signal (R) output to the level shift
R24
GNDSINK
-
Ground terminal
R25
VDD_L0
-
Power supply terminal
R26
NC
-
Not used
T1
SDR_CKE0
O
Clock enable signal output to the 256Mbit SD-RAM
T2
NC
-
Not used
T3
SDR_CSZ0
O
Chip select signal output to the 256Mbit SD-RAM
T4
SDR_BA1
O
Bank address signal output to the 256Mbit SD-RAM
T5
SDR_RASZ
O
Row address strobe signal output to the 256Mbit SD-RAM
T8
NC
-
Not used
T9
GND
-
Ground terminal
T10
NC
-
Not used
T17
U70_SOUT
O
Serial data output to the WM-port
T18
U70_SRIN
I
Serial data input from the WM-port
T19
GND
-
Ground terminal
T22
LCD_R5
O
Video signal (R) output to the level shift
T23
NC
-
Not used
T24
C_TMS
I
MS signal input terminal for JTAG Not used
T25
VLOG
O
Power supply output terminal
T26
CKO
O
Main system clock output terminal (11.2896MHz)
U1 to U5
SDR_A12 to
SDR_A8
O
Address signal output to the 256Mbit SD-RAM
U8
SDR_CASZ
O
Column address strobe signal output to the 256Mbit SD-RAM
U9
GND
-
Ground terminal
U10 to
U12
NC
-
Not used
U13
WAKEUP
O
Wake up signal output terminal
U14
NC
-
Not used
U15
L1_DET
-
Not used
U16
ERR_RST_REQZ
-
Not used
U17
NC
-
Not used
U18
REFCLKO
O
Master clock signal output to the D/A converter
U19
NC
-
Not used
U22
C_TDO
O
Data output terminal for JTAG Not used
U23
VLOGIN
I
Power supply voltage input terminal
36
NW-A805/A806/A808/NWZ-A815/A816/A818
Pin No.
Pin Name
I/O
Description
U24
C_TCK
I
Clock signal input terminal for JTAG Not used
U25
VPLL
O
Power supply voltage output terminal
U26
CKI
I
Main system clock input terminal (11.2896MHz)
V1 to V3
IO_A
-
Not used
V4, V5,
V8
SDR_A6, SDR_A5,
SDR_A7
O
Address signal output to the 256Mbit SD-RAM
V9
GND
-
Ground terminal
V10
CHG_XCHGEN
O
Charge enable signal output to the charge control
V11
NC
-
Not used
V12 to
V15
GND
-
Ground terminal
V16
DSP_DET
-
Not used
V17
LCD_BLTCTL
O
Control signal output to the LCD back light driver
V18, V19
NC
-
Not used
V22
C_RTCK
I
Clock signal input terminal for JTAG Not used
V23
C_TRSTZ
I
Reset signal input terminal for JTAG Not used
V24
VPLLIN
I
Power supply voltage input terminal
V25
VDSPIN
I
Power supply voltage input terminal
V26
VDSP
-
Not used
W1
IOGND
-
Ground terminal
W2
LCD_PCI
O
PCI signal output to the liquid crystal display
W3
LCD_PON
O
PON signal output to the liquid crystal display
W4, W5
SDR_A4, SDR_A3
O
Address signal output to the 256Mbit SD-RAM
W8
CHG_PEN2
O
Charge enable signal output to the charge control
W9
GND
-
Ground terminal
W10
NC
-
Not used
W11 to
W18
GND
-
Ground terminal
W19
WR_ERR
-
Not used
W22
NC
-
Not used
W23
C_TDI
I
Data input terminal for JTAG Not used
W24, W25
IO_B
-
Not used
W26
VLO
O
Power supply voltage output terminal
Y1
IOVDD
-
Power supply terminal
Y2
CHG_ICTL
O
Charge on/off control signal output to the charge control
Y3
HP_XMUTE
O
Analog muting on/off control signal output terminal
Y4, Y5
SDR_A2, SDR_A1
O
Address signal output to the 256Mbit SD-RAM
Y22, Y23
TM1, TM0
-
Not used
Y24, Y25
VDD_DSP
-
Power supply terminal
Y26
VHP
O
Power supply voltage output terminal
AA1
CRD_LINEOUT
O
Selection signal output to the headphone/line selecter
AA2
WAKEUP_INT
I
Wake up signal input terminal
AA3
GPIO9
-
Not used
AA4
SDR_A0
O
Address signal output to the 256Mbit SD-RAM
AA5
SDR_CLK
O
Clock signal output to the 256Mbit SD-RAM
AA22,
AA23
GND
-
Ground terminal
AA24
TM2
-
Not used
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