Sony MHC-GNX600 (serv.man2) Service Manual ▷ View online
53
HCD-GNX600
– Placa CD –
IC301 TC94A34FG-002
33
34
35
36
37
38
39
40
41
42
1
8
43
61
62
63
64
60
59
56
52
50
47
46
45
44
48
49
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
9
10
11
2
3
4
5
6
7
58
57
55
53
51
12
13
14
15
16
54
CS/RAS/SDO2
AD15/CAS/PD12
SDO3/OE
WE/SDO1
PIO7/B
US3/IO7
PIO6/FI3/B
US2/IO7
PIO5/FI2/B
US1/IO5
PIO4/FI1/B
US0/IO4
Bus
Switch
PO11/BUCK/AD14
PO10/CCE/AD13
PO9/AD12
PO08/AD11
Gener
al
In/Output P
or
t
Address Calc.
2sets
Y-
P
ointer
register
C-P
ointer
register
X-P
ointer
register
VDDM
SRMSTB
VDDT
AD10
AD9
ERAM
2k w
ord
CRAM
4k w
ord
CR
OM
4k w
ord
YRAM
4k w
ord
XRAM
4k w
ord
SRAM/
DRAM I/F
SRAM I/F
1Mbit
SRAM
X-Bus
Y
-Bus
PO07/AD7
PO06/AD6
PO05/AD5
AD8
VC0
Timing
Generator
PRAM
Instr
uction
Decoder
Prog
ram
Control
MCU
. I/F
register
XO • X1 • X2
Y0 •
Y1 •
Y2
MX
MY
MZ
MA
C
A0
A1
AX
A
Y
ALU
A2
A3
DIT
round & limit
round & limit
A
udio I/F
LRCKIA
BCKIA
SDI0
LRCKO
BCKO
SDO0
VSS
VDDT
MIACK
MICK
MIDIO
MILP
MICS
STANBY
RESET
VDDP
AD4/PO04
AD3/PO03
AD2/PO02
AD1/PO01
AD0/PO00
VSS
VDD
CK
O/PO13/AD16
VDDX
XO
TEST
VCOI
VSSX
XI
MIMD
VSSP
PIO3/IO3
PIO2/IO2
PIO1/SDI3/IO1
PIO0/SDI2/IO0
VSS
CKI/CLOCK/IRQ/FIO
VDD
TXO
SFSY/LRCKIB
SBSY/BCKIB
SDI1/D
A
T
A
POM
Sub code
I/F
CDP Cont
I/F
54
HCD-GNX600
– Placa ADC –
IC11,12 PCM1803DBR
FMT 1
DELTA-SIGMA
MODULATOR
L IN
1
R IN
2
V_REF_1 3
V_REF_2 4
18
SCKI
15
MODE 0
19
MODE 1
20
REFERENCE
PDWN
7
BYPASS 8
VDD
14
VCC 5
AGND 6
DGND
13
POWER SUPPLY
CLOCK AND TIMING CONTROL
LRCK 10
DOUT
12
FSYNC
9
BCK
11
FMT 0
17
TEST
16
x1/64, x1/128
DECIMATION
FILTER
WITH
HIGH-PASS FILTER
MODE/
FORMAT
CONTROL
SERIAL
INTERFACE
DELTA-SIGMA
MODULATOR
– BoardSMASTER –
IC500,600 CXD9843AR
S
P
SAMPLING RATE
CONVERTER
DF2
DF1
GAIN
CONTROL
FILTER
&
LOW CUT FILTER
SERIAL
CONTROL
LINER
INTERPOLATOR
∆ ∑ CONVERTER
XVSS
PWM
INIT/MUTE
CLOCK GENERATOR
CLOCK GENERATOR
(SECONDARY CLOCK SYSTEM)
1
VSUBC
2
VSSR
VSSL
VSSL
VSSR
3
OUTR2
OUTL2
OUTR1
OUTL1
4
VDDR
DVDD
DVSS
VDDL
5
6
7
8
XOVSS
XOVDD
9
XFSOOUT
10 11
NSPMUTE
12
SOFTMUTE
13
PGMUTE
SCSHIFT
14
SCDT
15
SCLATCH
OVF FLAGR
OVF FLAGL
16
SFLAG
INIT
17
MCKSEL
18
LRCK
19
BCK
20
D
ATA
BFVDD
BFVSS
TEST
DVDD
XFSIIN
21
42
43
41
40
39
38
37
XFSOIN
36
XVDD
35
HPVDDL
34
HPOUTL2
33
HPVSSL
32 31
HPVDDR
30
HPOUTR1
HPOUTL1
29 28
HPVSSR
27 26 25
HPOUTR2
24
FSOI
23
FSOCKO
22
44
45
46
47
48
(PRIMARY CLOCK SYSTTEM)
55
HCD-GNX600
7-26. Descrições das Funções de Pinos de IC
• IC101 CXD3059AR (RF AMP,DSP,DAC) (PLACA CD)
Pin No.
Pin Name
I/O
Description
1
MIRR
I/O
Not used (Open)
2
DFCT
I/O
Not used (Open)
3
FOK
I/O
Not used (Open)
4
VSS
–
Ground terminal
5
LOCK
I/O
Not used (Open)
6
MDP
O
Spindle motor servo control signal output
7
SSTP
I
Disc innermost detection signal input
8
IOVSS1
–
Ground terminal
9
SFDR
O
Sled drive signal output
10
SRDR
O
Sled drive signal output
11
TFDR
O
Tracking drive signal output
12
TRDR
O
Tracking drive signal output
13
FFDR
O
Focus drive signal output
14
FRDR
O
Focus drive signal output
15
IOVDD1
–
Power supply terminal (+3.3V)
16
AVDD0
–
Power supply terminal (+3.3V)
17
AVSS0
–
Ground terminal
18
NC
–
Not used (Open)
19
E
I
E signal input
20
F
I
F signal input
21
TEI
I
Tracking error signal input
22
TEO
O
Tracking error signal output
23
FEI
I
Focus error signal input
24
FEO
O
Focus error signal output
25
VC
O
Center voltage output from RF amplifier block
26
A
I
A signal input
27
B
I
B signal input
28
C
I
C signal input
29
D
I
D signal input
30
NC
–
Not used (Open)
31
AVDD4
–
Power supply terminal (+3.3V)
32
RFDCO
O
RFDC signal output (Open)
33
PDSENS
I
Reference voltage terminal
34
AC_SUM
O
RFAC summing amplifier signal output
35
EG_IN
I
Equalizer circuit signal input
36
LD
O
APC LD drive signal output
37
PD
I
APC PD signal input
38
NC
–
Not used (Open)
39
RFC
I
Equalizer cut-off frequency adjustment terminal
40
AVSS4
–
Ground terminal
41
RFACO
O
RFAC signal output
42
RFACI
I
RFAC signal input or EFM signal input
43
AVDD3
–
Power supply terminal (+3.3V)
44
BIAS
I
Asymmetry circuit constant current input
45
ASYI
I
Asymmetry comparator voltage input
46
ASYO
O
EFM full-swing signal output
47
VPCO
O
Not used (Open)
48
VCTL
I
Wide-band EFM PLL VCO2 control voltage input
56
HCD-GNX600
Pin No.
Pin Name
I/O
Description
49
AVSS3
–
Ground terminal
50
CLTV
I
Multiplier VCO1 control voltage input
51
FILO
O
Master PLL (slave = digital PLL) filter signal output
52
FILI
I
Master PLL filter signal input
53
PCO
O
Master PLL charge pump signal output
54
AVDD5
–
Power supply terminal (+3.3V)
55
DDVROUT
O
DC/DC converter output (+2.5V)
56
DDVRSEN
I
DC/DC converter output voltage monitor signal input
57
AVSS5
–
Ground terminal
58
DDCR
I
DC/DC converter reset signal input
59
NC
–
Not used (Open)
60
BCKI
I
D/A interface bit clock input
61
PCMDI
I
D/A interface serial data input
62
LRCKl
I
D/A interface LR clock input
63
LRCK
O
D/A interface LR clock output f = Fs
64
VSS
–
Ground terminal
65
PCMD
O
D/A interface serial data output
66
BCK
O
D/A interface bit clock output
67
VDD
–
Power supply terminal (+2.5V)
68
EMPH
O
High when the playback disc has emphasis, low it has not
69
EMPHI
I
High when de-emphasis is ON, low when input OFF
70
IOVDD2
–
Power supply terminal (+3.3V)
71
DOUT
O
Digital Out signal output
72
TEST
I
Test terminal (Connected to ground)
73
TEST1
I
Test terminal (Connected to ground)
74
IOVSS2
–
Ground terminal
75
NC
–
Not used (Open)
76
XVSS
–
Ground terminal
77
XTAO
O
Crystal oscillation circuit signal output
78
XTAI
I
Crystal oscillation circuit signal input
79
XVDD
–
Power supply terminal (+2.5V)
80
AVDD1
–
Power supply terminal (+3.3V)
81
AOUT1
O
L-ch analog signal output
82
VREFL
O
L-ch reference voltage output
83
AVSS1
–
Ground terminal
84
AVSS2
–
Ground terminal
85
VREFR
O
R-ch reference voltage output
86
AOUT2
O
R-ch analog signal output
87
AVDD2
–
Power supply terminal (+3.3V)
88
NC
–
Not used (Open)
89
IOVDD0
–
Power supply terminal (+3.3V)
90
RMUT
O
Not used (Open)
91
LMUT
O
Not used (Open)
92
NC
–
Not used (Open)
93
XTSL
I
Crystal selection signal input (Pull down)
94
IOVSS0
–
Ground terminal
95
XTACN
I
Oscillation circuit control signal input (“H”: self-oscillation, “L”: oscillation stop)
96
SQSO
O
Not used (Open)
97
SQCK
I
SQSO readout clock input (Connected to +VDD(+3.3V))
98
SBSO
O
Not used (Open)
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