Sony MDS-W1 Service Manual ▷ View online
– 107 –
Function
Pin No.
Pin Name
I/O
48
49
50, 51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
D1
D0
D2, D3
MVCI
ASYO
ASYI
AVDD
BIAS
RFI
AVSS
PCO
FILI
FILO
CLTV
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
AVDD
ADRT
ADRB
AVSS
SE
TE
DCHG
APC
ADFG
F0CNT
XLRF
CKRF
DTRF
APCREF
TEST0
TRDR
Data input/output for DRAM
Clock input from an external VCO (Fixed at “L”)
Playback EFM duplex signal output
Playback EFM comparator slice level input
+3V power supply (Analog)
Playback EFM comparator bias current input
Playback EFM RF signal input
Ground (Analog)
Phase comparison output for the recording/playback EFM master PLL
Filter input for the recording/playback EFM master PLL
Filter output for the recording/playback EFM master PLL
Internal VCO control voltage input for the recording/playback EFM master PLL
Light amount signal peak hold input from the CXA2523AR
Light amount signal bottom hold input from the CXA2523AR
Light amount signal input from the CXA2523AR
Focus error signal input from the CXA2523AR
Auxiliary A/D input
Middle point voltage (+1.5V) input from the CXA2523AR
Monitor output of the A/D converter input signal (Not used)
+3V power supply (Analog)
A/D converter operational range upper limit voltage input (Fixed at “H”)
A/D converter operational range lower limit voltage input (Fixed at “L”)
Ground (Analog)
Sled error signal input from the CXA2523AR
Tracking error signal input from the CXA2523AR
Connected to +3V power supply
Error signal input for the laser digital APC (Fixed at “L”)
ADIP duplex FM signal input from the CXA2523AR (22.05 ± 1 kHz)
Filter f
0
control output to the CXA2523AR
Control latch output to the CXA2523AR
Control clock output to the CXA2523AR
Control data output to the CXA2523AR
Reference PWM output for the laser APC
Test terminal
Tracking servo drive PWM output (–)
I/O
I/O
I/O
I (S)
O
I (A)
—
I (A)
I (A)
—
O (3)
I (A)
O (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
—
I (A)
I (A)
—
I (A)
I (A)
I (A)
I (A)
I (S)
O
O
O
O
O
O
O
• Abbreviation
EFM: Eight to Fourteen Modulation
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
– 108 –
Function
Pin No.
Pin Name
I/O
86
87
88
89
90
91
92
93
94
95
96 to 98
99
100
TFDR
DVDD
FFDR
FRDR
FS4
SRDR
SFDR
SPRD
SPFD
FGIN
TEST1 to TEST3
DVSS
EFMO
O
—
O
O
O
O
O
O
O
I (S)
I
—
O
Tracking servo drive PWM output (+)
+3V power supply (Digital)
Focus servo drive PWM output (+)
Focus servo drive PWM output (–)
176.4 kHz clock signal output (X’tal) (Not used)
Sled servo drive PWM output (–)
Sled servo drive PWM output (+)
Spindle servo drive PWM output (–)
Spindle servo drive PWM output (+)
Test input (Fixed at “L”)
Ground (Digital)
EFM output when recording
• Abbreviation
EFM: Eight to Fourteen Modulation
– 109 –
Pin No.
Pin Name
I/O
Function
• IC701 (DECK A) System Control (M30610MCA-254FP)
1, 2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21, 22
23, 24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40, 41
42, 43
44, 45
46
47
48
49
50
51
52
53
54
—
DA OUT0
DA OUT1
SQSY
—
—
BYTE
CNVSS
XIN-T
XOUT-T
SYSTEM-RESET
XOUT
GND
XIN
VCC
NMI
DQSY
POWER-DOWN
XINT
JOG 1, JOG 0
—
—
MEC-CS
MEC-CTS
MEC-CLK
MEC-RDT
MEC-WDT
SWDT
SRDT
SCLK
—
MAS-WDT
MAS-RDT
MAS-CLK
MAS-RTS
MAS-CS
—
DEM 1, DEM 0
DIF 1, DIF 0
DUB/SOURCE-SEL
AMUTE
ANA/DUB-SEL
OUTPUT-SEL
STB
—
DISC. IN-SW
OUT-SW
—
O
O
O
I
O
O
I
—
O
O
I
O
—
I
—
I
I
I
I
O
O
O
O
O
O
I
O
O
I
O
O
O
I
O
O
O
O
O
O
O
O
O
O
O
O
I
I
O
Not used
ATP address sync or subcode Q sync input from CXD2654R
Not used
Not used
Input switched by data bus (Connected to ground)
Ground
Not used
System reset signal input
“L”:Reset
Main click output (7.0 MHz)
Ground
Main clock input (7.0 MHz)
+3.3V power supply
Digital in U-bit from CXD2654R
CD format subcode Q sync input
Power down signal input
“L”:Power down
Interrupt status signal input from CXD26524R
Not used
Not used
Chip select signal output
Chip select signal output
Serial CTS signal output
Serial clock signal output
Serial data in signal input
Serial data out signal output
Write data signal output to serial bus
Read data signal input from serial bus
Clock signal output to serial bus
Not used
Serial data out signal output
Serial data in signal input
Serial clock signal output
Master reset signal output
Master chip select signal output
Not used
D/A deemphasis setting signal output
Not used
DUBBING SOURCE setting signal output
“L”:Deck A, “H”:Deck B
Line mute signal output
“H”:ON, “L”:OFF
A/D input selection signal output
“H”:Analog
“L”:DUB
OUTPUT A/B selection signal output
“L”:Deck A
“H”:Deck B
Strobe signal output to the power supply circuit
“H”:Power ON
Not used
Detection signal input from the disc detection switch
Detection signal input from the loading out switch
“L”:Load out
Not used
– 110 –
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94, 95
96
97
98
99
100
Pin No.
Pin Name
I/O
Function
O
O
O
O
I
I
O
O
O
—
I
I
O
I
O
I
O
I
O
I
O
I
I
I/O
O
O
I
I
I
O
O
O
O
O
O
O
I
I
O
O
—
O
—
—
O
Loading motor control output
Loading motor voltage control output
Loading motor control output
Not used
Detection signal input from the recording position detection switch
Detection signal input from the playback position detection switch
Not used
+3.3V power supply
Gain switch signal output
Ground
Internal status (SENS) input from CXD2654R
Track jump signal input from CXD2654R
Reset signal input to CXD2654R, motor driver
“L”:Reset
Monitoring of command execution status from CXD2654R
Laser power ON/OFF control output
Disc reflection detection signal input
“H”:Low reflection rate disc
Latch signal input to serial bus
Recording prevention tab detection input from protect detection switch
High frequency superimpose ON/OFF control output
Detection signal input from the limit in switch
“L”:Sled limit in
BD write power ON/OFF signal output
Spindle servo lock status monitoring input from CXD2654R
Focus OK signal input from CXD2654R
Data signal input/output with backup memory
Clock signal output to backup memory
Write data transmission timing output to CXD2654R
Destination selection pin for clock (Not used)
Deck A/B selection signal input
“H”: Deck A, “L”: Deck B
D/A data format setting signal output
Not used
A/D data mute ON/OFF signal output
A/D MCLK select signal output
“L”: 256fs, “H”: 512fs
D/A soft mute ON/OFF signal output
A/D LRCK, BCK select signal output
“L”: LRCK, BCK of Deck A, “H”: LRCK, BCK OF Deck B
D/A reset signal input
“L”:Reset
A/D reset signal input
“L”:Reset
Not used
Analog ground
Not used
+3.3V power supply
Not used
LD-OUT
LD-LOW
LD-IN
—
REC. P
PB. P
—
VCC
GAIN. SW
GND
SENS
SHCK (MNT1)
DIG-RST
BUSY (MNT2)
LDON
REFLECT
XLATCH
PROTECT
MOD
LIMIT-IN
WPOWER
SLOCK(MNT3)
FOK (MNT0)
SDA
SCL
SCTX
C. SET0
C. SET1
DECK A/B-SEL
DI-SEL1
DI-SEL0
—
ADDT-MUTE
W. SPEED-SEL
SMUTE
AD CLK-SEL
DA-RESET
AD-RESET
(KEY3)
(KEY2) (KEY1)
AVSS
(KEY0)
VREF
+3.3V
—
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