Sony MDS-W1 Service Manual ▷ View online
– 103 –
IC311, 316, 521 SN74HC157APW-E20
• Jack (2/2) section
IC501 SN74HCU04AN
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
GND
• Main section
IC301 SN74HCU04APW-E20
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
GND
IC306 SN74HC74APW-E20
14
13
11
10
9
8
VCC
12
1
3
2
4
6
7
GND
5
PR
CLR
D
Q
Q
CK
PR
CLR
D
Q
Q
CK
1
2
3
4
5
6
7
8
9
10
16
15
14
13
12
11
1A
1B
1Y
2Y
2B
2Y
4A
4B
4Y
3A
3B
O
S
GND
3Y
VCC
3Y
3B
3A
4Y
4B
4A
STROEE
SELECT
1A
1B
1Y
2A
2B
2Y
IC331, 351 AK4321-VF-E2
CTF
SCF
CLOCK OSC/DIVIDER
∆Σ
MODULATOR
SERIAL INPUT
INTERFACE
8
×
INTERPOLATOR
DE-EMPHASIS
CONTROL
8
×
INTERPOLATOR
∆Σ
MODULATOR
CTF
SCF
1
2
3
4
5
6
7
8
9
10
20
19 18 17 16 15
14
13
12
11
21
22
23
24
TTL
DZF
VREF
AVSS
AVDD
VCOM
AOUTL
AOUTR
BVDD
DIF1
DIF0
DEM1
CKS
DVDD
DVSS
XTO
XTI
PD
BICK
SDATA
LRCK
SMUTE
DFS
DEMO
IC321,851, 861 TC74HCT7007AF (EL)
14
4Y
4A
5Y
5A
6Y
6A
VCC
1A
1Y
2A
2Y
3A
3Y
GND
13
12
11
10
9
8
1
2
3
4
5
6
7
IC461 AK5352-VF-E2
18
23
15
17
22
24
13
12
4
5
19
20
21
8
10
11
14
SCLK
SMODE1
SMODE2
MCLK
CMODE
VB
DGND
VD
VA
AGND
VREF
AINL+
AINL–
AINR+
AINR–
LRCK
FSYNC
SDATA
TST1
9
HPFE
16
PD
TST2
TST3
TST4
Clock Divider
Voltage
Reference
Modulator
Serial Output
Interface
Digital Decimation
Filter
3
6
7
1
2
Modulator
– 104 –
IC471, 831 SN74LVC125APW-E20
1
2
3
1A
1Y
1 OE
4
5
6
2A
2Y
2 OE
7
GND
10
9
8
3A
3Y
3 OE
13
12
11
4A
4Y
4 OE
14 VCC
IC491 TC7W74FU (TE12R)
6
CLR
7
PR
8
VCC
5
Q
R
S
Q
3
Q
2
D
4
GND
1
CK
Q
D
C
IC511, 516 SN74HC153APW-E20
16
1
2
3
4
5
6
7
8
15
14
13
12
2C3
2C2
B
A
B
A
2C1
2C0
2Y
1C3
1C2
1C1
1C0
1Y
V
CC
2C3
2C2
2C1
2C0
DATA INPUTS
DATA INPUTS
STROBE
2G
STROBE
1G
B
SELECT
1C3
1C2
1C1
1C0 OUTPUT
1Y
GND
A
SELECT
OUTPUT
2Y
2G
11
10
9
1G
B
A
B
A
IC751, 951 LB1830M-S-TE-L
1
LOGIC
PREDRIVER
VREF
2
3
4
5
10
9
8
7
6
IN2
IN1
VM
VREF
VCONT
VCC
OUT2
GND
OUT1 VS
IC991 TC4W53FU-TE12L
8
7
6
5
1
2
3
4
VCC
CH1
CH0
ADR
COM
INH
VEE
VSS
• Power section
IC101 LA5632
1
–
+
12
DELAY
CIRCUIT
VREF
DELAY
CIRCUIT
3.3V
PH5
STBY
V
CC
ANA5
SYS3.3
B.BAK
AC
CD1
P. DOWN
GND
CD2
S. RESET
–
+
–
+
–
+
–
+
–
+
2
3
4
5
6
7
8
9
10
11
– 105 –
6-24. IC PIN FUNCTIONS
• IC101 RF Amplifier (CXA2523AR)
Pin No.
Pin Name
I/O
Function
I
J
VC
A to F
PD
APC
APCREF
GND
TEMPI
TEMPR
SWDT
SCLK
XLAT
XSTBY
F0CNT
VREF
EQADJ
3TADJ
Vcc
WBLADJ
TE
CSLED
SE
ADFM
ADIN
ADAGC
ADFG
AUX
FE
ABCD
BOTM
PEAK
RF
RFAGC
AGCI
COMPO
COMPP
ADDC
OPO
OPN
RFO
MORFI
MORFO
I
I
O
I
I
O
I
—
I
O
I
I
I
I
I
O
I/O
I/O
—
I/O
O
—
O
O
I
—
O
O
O
O
O
O
O
—
I
O
I
I/O
O
I
O
I
O
I-V converted RF signal I input
I-V converted RF signal J input
Middle point voltage (+1.5V) generation output
Signal input from the optical pick-up detector
Light amount monitor input
Laser APC output
Reference voltage input for setting laser power
Ground
Temperature sensor connection
Reference voltage output for the temperature sensor
Serial data input from the CXD2654R
Serial clock input from the CXD2654R
Latch signal input from the CXD2654R
“L”: Latch
Stand by signal input
“L”: Stand by
Center frequency control voltage input of BPF22, BPF3T, EQ from the CXD2650R or
CXD2654R
Reference voltage output (Not used)
Center frequency setting pin for the internal circuit EQ
Center frequency setting pin for the internal circuit BPF3T
+3V power supply
Center frequency setting pin for the internal circuit BPF22
Tracking error signal output to the CXD2654R
External capacitor connection pin for the sled error signal LPF
Sled error signal output to the CXD2654R
FM signal output of ADIP
ADIP signal comparator input
ADFM is connected with AC coupling
External capacitor connection pin for AGC of ADIP
ADIP duplex signal output to the CXD2654R
I
3
signal/temperature signal output to the CXD2654R
(Switching with a serial command)
Focus error signal output to the CXD2654R
Light amount signal output to the CXD2654R
RF/ABCD bottom hold signal output to the CXD2654R
RF/ABCD peak hold signal output to the CXD2654R
RF equalizer output to the CXD2654R
External capacitor connection pin for the RF AGC circuit
Input to the RF AGC circuit
The RF amplifier output is input with AC coupling
User comparator output (Not used)
User comparator input (Fixed at “L”)
External capacitor pin for cutting the low band of the ADIP amplifier
User operation amplifier output (Not used)
User operation amplifier inversion input (Fixed at “L”)
RF amplifier output
Groove RF signal is input with AC coupling
Groove RF signal output
1
2
3
4 to 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
• Abbreviation
APC: Auto Power Control
AGC: Auto Gain Control
AGC: Auto Gain Control
– 106 –
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 to 34
35
36 to 40
41
42
43
44
45
46
47
• IC121 Digital Signal Processor, Digital Servo Signal Processor, EFM/ACIRC Encoder/Decoder,
Shock-proof Memory Controller, ATRAC Encoder/Decoder, 2M Bit DRAM (CXD2654R)
Function
Pin No.
Pin Name
I/O
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DIN0
DIN1
DOUT
DADTI
LRCKI
XBCKI
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
I
I
O
I
I
I
O
I
I
I
I
O
O
O
O
—
O
O
O
O
—
O
O
O
O
O
FOK signal output to the system control (monitor output)
“H” is output when focus is on
Track jump detection signal output to the system control (monitor output)
Monitor 2 output to the system control (monitor output)
Monitor 3 output to the system control (monitor output)
Writing data signal input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Reading data signal output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control
“L”: Reset
Subcode Q sync (SCOR) output to the system control
“L” is output every 13.3 msec. Almost all, “H” is output
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system
control
Laser power switching input from the system control
“H”: Recording, “L”: Playback
Interrupt status output to the system control
Recording data output enable input from the system control
System clock input
System clock output (Not used)
System clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (Pull up at “H”)
Digital audio input (Optical input)
Digital audio output (Optical output)
Serial data input
LR clock input
“H” : Lch, “L” : R ch
Serial data clock input
Data input from the A/D converter
Data output to the D/A converter
LR clock output for the A/D and D/A converter (44.1 kHz)
Bit clock output to the A/D and D/A converter (2.8224 MHz)
11.2896 MHz clock output (Not used)
+3V power supply (Digital)
DRAM address output
DRAM address output (Not used)
DRAM address output
DRAM address output (Not used)
Ground (Digital)
Output enable output for DRAM
CAS signal output for DRAM
Address output for DRAM
RAS signal output for DRAM
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
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