Sony MDS-SP55 Service Manual ▷ View online
45
6-13. IC PIN FUNCTIONS
• IC101 RF Amplifier (CXA2523AR) (BD board)
Pin No.
Pin Name
I/O
Function
I
J
VC
A to F
PD
APC
APCREF
GND
TEMPI
TEMPR
SWDT
SCLK
XLAT
XSTBY
F0CNT
VREF
EQADJ
3TADJ
Vcc
WBLADJ
TE
CSLED
SE
ADFM
ADIN
ADAGC
ADFG
AUX
FE
ABCD
BOTM
PEAK
RF
RFAGC
AGCI
COMPO
COMPP
ADDC
OPO
OPN
RFO
MORFI
MORFO
I
I
O
I
I
O
I
—
I
O
I
I
I
I
I
O
I/O
I/O
—
I/O
O
—
O
O
I
—
O
O
O
O
O
O
O
—
I
O
I
I/O
O
I
O
I
O
I-V converted RF signal I input
I-V converted RF signal J input
Middle point voltage (+1.5V) generation output
Signal input from the optical pick-up detector
Light amount monitor input
Laser APC output
Reference voltage input for setting laser power
Ground
Temperature sensor connection
Reference voltage output for the temperature sensor
Serial data input from the CXD2650R or CXD2652AR
Serial clock input from the CXD2650R or CXD2652AR
Latch signal input from the CXD2650R or CXD2652AR
“L”: Latch
Stand by signal input
“L”: Stand by
Center frequency control voltage input of BPF22, BPF3T, EQ from the CXD2650R or
CXD2652AR
Reference voltage output (Not used)
Center frequency setting pin for the internal circuit EQ
Center frequency setting pin for the internal circuit BPF3T
+3V power supply
Center frequency setting pin for the internal circuit BPF22
Tracking error signal output to the CXD2650R or CXD2652AR
External capacitor connection pin for the sled error signal LPF
Sled error signal output to the CXD2650R or CXD2652AR
FM signal output of ADIP
ADIP signal comparator input
ADFM is connected with AC coupling
External capacitor connection pin for AGC of ADIP
ADIP duplex signal output to the CXD2650R or CXD2652AR
I
3
signal/temperature signal output to the CXD2650R or CXD2652AR
(Switching with a serial command)
Focus error signal output to the CXD2650R or CXD2652AR
Light amount signal output to the CXD2650R or CXD2652AR
RF/ABCD bottom hold signal output to the CXD2650R or CXD2652AR
RF/ABCD peak hold signal output to the CXD2650R or CXD2652AR
RF equalizer output to the CXD2650R or CXD2652AR
External capacitor connection pin for the RF AGC circuit
Input to the RF AGC circuit
The RF amplifier output is input with AC coupling
User comparator output (Not used)
User comparator input (Fixed at “L”)
External capacitor pin for cutting the low band of the ADIP amplifier
User operation amplifier output (Not used)
User operation amplifier inversion input (Fixed at “L”)
RF amplifier output
Groove RF signal is input with AC coupling
Groove RF signal output
1
2
3
4 to 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
• Abbreviation
APC: Auto Power Control
AGC: Auto Gain Control
AGC: Auto Gain Control
46
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 to 34
35
36 to 40
41
42
43
44
45
46
47
48
49
50, 51
• IC121 Digital Signal Processor, Digital Servo Signal Processor, EFM/ACIRC Encoder/Decoder,
Shock-proof Memory Controller, ATRAC Encoder/Decoder, 2M Bit DRAM (CXD2654R) (BD board)
Function
Pin No.
Pin Name
I/O
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DIN0
DIN1
DOUT
DADTI
LRCKI
XBCKI
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
D1
D0
D2, D3
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
I
I
O
I
I
I
O
I
I
I
I
O
O
O
O
—
O
O
O
O
—
O
O
O
O
O
I/O
I/O
I/O
FOK signal output to the system control (monitor output)
“H” is output when focus is on
Track jump detection signal output to the system control (monitor output)
Monitor 2 output to the system control (monitor output)
Monitor 3 output to the system control (monitor output)
Writing data signal input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Reading data signal output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control
“L”: Reset
Subcode Q sync (SCOR) output to the system control
“L” is output every 13.3 msec. Almost all, “H” is output
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system
control
Laser power switching input from the system control
“H”: Recording, “L”: Playback
Interrupt status output to the system control
Recording data output enable input from the system control
System clock input (512Fs=22.5792 MHz)
System clock output (512Fs=22.5792 MHz) (Not used)
System clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (Fixed at “H”)
Digital audio input (Optical input)
Digital audio input (Optical input)
Digital audio output (Optical output)
Serial data input
LR clock input
“H” : Lch, “L” : R ch
Serial data clock input
Data input from the A/D converter
Data output to the D/A converter
LR clock output for the A/D and D/A converter (44.1 kHz)
Bit clock output to the A/D and D/A converter (2.8224 MHz)
11.2896 MHz clock output (Not used)
+3V power supply (Digital)
DRAM address output
DRAM address output (Not used)
DRAM address output
DRAM address output (Not used)
Ground (Digital)
Output enable output for DRAM
CAS signal output for DRAM
Address output for DRAM
RAS signal output for DRAM
Write enable signal output for DRAM (Used : CXD2652AR, Not used : CXD2650R)
Data input/output for DRAM
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
47
Function
Pin No.
Pin Name
I/O
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96 to 98
99
100
MVCI
ASYO
ASYI
AVDD
BIAS
RFI
AVSS
PCO
FILI
FILO
CLTV
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
AVDD
ADRT
ADRB
AVSS
SE
TE
DCHG
APC
ADFG
F0CNT
XLRF
CKRF
DTRF
APCREF
TEST0
TRDR
TFDR
DVDD
FFDR
FRDR
FS4
SRDR
SFDR
SPRD
SPFD
FGIN
TEST1 to TEST3
DVSS
EFMO
Clock input from an external VCO (Fixed at “L”)
Playback EFM duplex signal output
Playback EFM comparator slice level input
+3V power supply (Analog)
Playback EFM comparator bias current input
Playback EFM RF signal input
Ground (Analog)
Phase comparison output for the recording/playback EFM master PLL
Filter input for the recording/playback EFM master PLL
Filter output for the recording/playback EFM master PLL
Internal VCO control voltage input for the recording/playback EFM master PLL
Light amount signal peak hold input from the CXA2523R
Light amount signal bottom hold input from the CXA2523R
Light amount signal input from the CXA2523R
Focus error signal input from the CXA2523R
Auxiliary A/D input
Middle point voltage (+1.5V) input from the CXA2523R
Monitor output of the A/D converter input signal (Not used)
+3V power supply (Analog)
A/D converter operational range upper limit voltage input (Fixed at “H”)
A/D converter operational range lower limit voltage input (Fixed at “L”)
Ground (Analog)
Sled error signal input from the CXA2523R
Tracking error signal input from the CXA2523R
Connected to +3V power supply
Error signal input for the laser digital APC (Fixed at “L”)
ADIP duplex FM signal input from the CXA2523R (22.05 ± 1 kHz)
Filter f
0
control output to the CXA2523R
Control latch output to the CXA2523R
Control clock output to the CXA2523R
Control data output to the CXA2523R
Reference PWM output for the laser APC
PWM output for the laser digital APC (Not used)
Tracking servo drive PWM output (–)
Tracking servo drive PWM output (+)
+3V power supply (Digital)
Focus servo drive PWM output (+)
Focus servo drive PWM output (–)
176.4 kHz clock signal output (X’tal) (Not used)
Sled servo drive PWM output (–)
Sled servo drive PWM output (+)
Spindle servo drive PWM output (–)
Spindle servo drive PWM output (+)
Test input (Fixed at “L”)
Ground (Digital)
EFM output when recording
I (S)
O
I (A)
—
I (A)
I (A)
—
O (3)
I (A)
O (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
—
I (A)
I (A)
—
I (A)
I (A)
I (A)
I (A)
I (S)
O
O
O
O
O
O
O
O
—
O
O
O
O
O
O
O
I (S)
I
—
O
• Abbreviation
EFM: Eight to Fourteen Modulation
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
O
I
O
O
O
O
O
I
I
I
O
I
O
—
I
—
I
I
I
O
O
O
O
O
O
O
I
I
I/O
I/O
O
O
O
O
O
I
O
O
I
I
O
O
I
I
O
O
O
O
O
O
MD WM LINK data out (Not used)
MD WM LINK clock in (Fixed at “L”)
LEVEL-L DA output (Not used)
LEVEL-R DA output (Not used)
LED DRIVER DATA output (Not used)
Not used
LED DRIVER CLOCK output (Not used)
Data bus switching (Fixed at “L”)
Pulled down to “L”
Not used
System reset
Main clock output (10 MHz)
Ground pin
Main clock output (10 MHz)
Power supply 3.3V
Not used (Fixed at “H”)
Power down detection
MD WM LINK SYNC input (Fixed at “L”)
I
2
C BUSY output (Not used)
AD/DA converter (IC201) clock out
AD/DA converter (IC201) data out
Not used
Elevator control up output (Not used)
Not used
Elevator control down output (Not used)
SUBQ, ADIP sync input
Reset switch detection signal
I
2
C clock
I
2
C data
FLD transmission data out (Not used)
Not used
FLD transmission data clock out (Not used)
FLD transmission data chip select out (Not used)
Serial data out
Serial data in
Serial clock out
Illumination output (“H”: Light up) (Not used)
Main sensor detection signal (Front panel open detection “H”: OPEN) (Fixed at “L”)
Sub sensor detection signal (Fixed at “L”)
Recording head control down output (Not used)
Recording head control up output (Not used)
Jog 0 input
Jog 1 input
MD WM LINK clock inverse signal output (Not used)
LED driver latch output
Optical input selection signal output (Not used)
A/D, D/A reset signal output (Not used)
Line mute (“L”: MUTE) (Not used)
Power on/off output (“H”: POW ON) (Not used)
WMOUT
WMCLK
LEVEL-L
LEVEL-R
LEDDATA
NC
LEDCLK
BYTE
CNVSS
XIN-T
XOUT-T
S.RST
XOUT
GND
XIN
3.3V
NMI
P.DOWN
WMSYNC
IICBUSY
L3CLK
L3DATA
NC
ELEUP
NC
ELEDOWN
SQSY
RESETSW
IICCLK
IICDATA
FLDATA
NC
FLCLK
FLCS
SWDT
SRDT
SCLK
ILLU
SENSOR
SENSOR2
HEADDOWN
HEADUP
JOG0
JOG1
WMINV
LEDLATCH
OPTSEL1
DARST
MUTE
STB
Pin No.
Pin Name
I/O
Function
• IC701 M30624MGA-A53FP MASTER CONTROL (MAIN BOARD)
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