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Model
MDS-SP55
Pages
57
Size
3.87 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
mds-sp55.pdf
Date

Sony MDS-SP55 Service Manual ▷ View online

29
5-13. ERROR RATE CHECK
5-13-1. CD Error Rate Check
Checking Procedure :
1. Load a check disc (MD) TDYS-1.
2. Rotate the  l L  knob and display “MD CPLAY MODE”.
3. Press the  ENTER/YES  button twice and display “MD CPLAY
MID”.
4. The display changes to “MD C1 = 
 AD = 
”.
5. Check that the C1 error rate is below 20.
6. Press the  MENU/NO  button, stop playback, press the   A  but-
ton, and remove the test disc.
5-13-2. MO Error Rate Check
Checking Procedure :
1. Load a test disc (MDW-74/GA-1).
2. Rotate the  l L  knob and display “MD CPLAY MODE”.
3. Press the  ENTER/YES  button and display “MD CPLAY MID”.
4. The display changes to “MD C1 = 
 AD = 
”.
5. If the C1 error rate is below 50, check that ADER is 00.
6. Press the  MENU/NO  button, stop playback, press the  A  but-
ton, and remove the test disc.
5-14. FOCUS BIAS CHECK
Change the focus bias and check the focus tolerance amount.
Checking Procedure :
1. Load a test disc (MDW-74/GA-1).
2. Rotate the  l L  knob and display “MD CPLAY MODE”.
3. Press the  ENTER/YES  button twice and display “MD CPLAY
MID”.
4. Press the  MENU/NO  button when “MD C1 = 
 AD = 
is displayed.
5. Rotate the  l L  knob and display “MD FBIAS CHECK”.
6. Press the  ENTER/YES  button and display “MD 
/
 c =
”.
The first four digits indicate the C1 error rate, the two digits
after [/] indicate ADER, and the 2 digits after [c =] indicate the
focus bias value.
Check that the C1 error is below 50 and ADER is below 2.
7. Press the  ENTER/YES  button and display “MD 
/
 b =
”.
Check that the C1 error is below 220 and ADER is below 2.
8. Press the  ENTER/YES  button and display “MD 
/
 a =
”.
Check that the C1 error is below 220 and ADER is below 2
9. Press the  MENU/NO  button, next press the  A  button, and
remove the continuously recorded disc.
Note 1 : If the C1 error and ADER are above other than the speci-
fied value at points a (step 8. in the above) or b (step 7. in
the above), the focus bias adjustment may not have been
carried out properly. Adjust perform the beginning again.
5-15. AUTO GAIN CONTROL OUTPUT LEVEL
ADJUSTMENT
Be sure to perform this adjustment when the pick-up is replaced.
If the adjustment results becomes “Adjust NG!”, the pick-up may
be faulty or the servo system circuits may be abnormal.
5-15-1. CD Auto Gain Control Output Level Adjustment
Adjusting Procedure :
1. Insert the check disc (MD) TDYS-1.
2. Rotate the  l L  knob to display “MD AG Set (CD)”.
3. When the  ENTER/YES  button is pressed, the adjustment will
be performed automatically.
“Complete!” will then be displayed momentarily when the value
is recorded in the non-volatile memory, after which the display
changes to “MD AG Set (CD)”.
4. Press the  A  button to remove the disc.
5-15-2. MO Auto Gain Control Output Level Adjustment
Adjusting Procedure :
1. Insert the reference disc (MDW-74/GA-1) for recording.
2. Rotate the  l L  knob to display “MD AG Set (MO)”.
3. When the  ENTER/YES  button is pressed, the adjustment will
be performed automatically.
“Complete!” will then be displayed momentarily when the value
is recorded in the non-volatile memory, after which the display
changes to “MD AG Set (MO)”.
4. Press the  A  button to remove the disc.
30
NOTE:
It is useful to use the jig. for checking the waveform.
(Refer to Servicing Note on page 7.)
[BD BOARD] (SIDE B)
CN110
NOTE
D101
I+3V
IOP
TE
VC
RF
GND
IC171
IC121
IC101
IC192
CN101
5-16. ADJUSTING POINTS AND CONNECTING POINTS
[BD BOARD] (SIDE A)
31
31
SECTION 6
DIAGRAMS
THIS NOTE IS COMMON FOR PRINTED WIRING
BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is printed
in each block.)
For schematic diagrams.
Note:
• All capacitors are in µF unless otherwise noted.  pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in 
 and 
1
/
4
 
W or less unless otherwise
specified.
f
: internal component.
C
: panel designation.
For printed wiring boards.
Note:
• X
: parts extracted from the component side.
• Y
: parts extracted from the conductor side.
a
: Through hole.
• b
: Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
U
: B+ Line.
V
: B– Line.
H
: adjustment for repair.
no mark : STOP
(
) : Play the test disc (TDYS-1)
<
> : REC
: Can not be measured.
• Voltages are taken with a VOM (Input impedance 10 M
).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
E
: PB
j
: REC
p
: PB (DIGITAL)
l
: REC (DIGITAL)
Note: The components identified by mark 
0
 or dotted line
with mark 
0
 are critical for safety.
Replace only with part number specified.
Caution:
Pattern face side: Parts on the pattern face side seen from the
(Side B)
pattern face are indicated.
Parts face side:
Parts on the parts face side seen from the
(Side A)
parts face are indicated.
• Indication of transistor
C
These are omitted
E
B
Q
C
These are omitted
E
B
WAVEFORMS
– BD (1/2) SECTION –
– MAIN SECTION –
4
5
6
7
8
IC121 
qh
 (OSCI)
1
2
3.0Vp-p
44.3nsec
3.2Vp-p
22.7
µ
sec
3.8Vp-p
354nsec
3.8Vp-p
88.6nsec
3.2Vp-p
5.67
µ
sec
3.2Vp-p
100nsec
1.7Vp-p
44.3nsec
– BD (2/2) SECTION –
IC121 
wj
 (LRCK)
IC121 
wk
 (XBCK)
IC121 
wl
 (FS256)
IC121 
o;
 (FS4)
IC701 
qd
 (XOUT)
IC601 
0
 (SYSCLK)
1.2Vp-p
1
 IC101 
ek
 RF PLAY MODE
3
 IC101 
ef
  FE 
       PLAY MODE
2
 IC101 
wh
  TE 
       PLAY MODE
1
µ
sec/div
approx 400mVp-p
approx 1.5Vp-p
32
32
MDS-SP55
HR901
OVER WRITE
HEAD
HEAD
DRIVE
Q181,182
3
6
1
2
FILTER
PCO
FILI
FILO
CLTV
PLL
EFM,
ACIRC,
ENCODER/
DECODER
RF AGC & EQ
AGCI
RFO
MORFI
MORFO
RF AMP
1
2
BPF
P-P
AT
AMP
BPF
ADAGC
VC
ANALOG
MUX
27
16
17
18
SERIAL
PARALLEL
DECODER
VICONV
20
25
22 23
4
5
6
7
8
9
IV AMP
IV AMP
E-F
BALANCE
14
15
3
VCC
VC
D101
12
11
10
LASER ON
SW
Q101
PD
APC
Q162,163
HF
MODULE
HF MODULE
SW
IC103,Q102-104
TRACKING
COIL
FOCUS
COIL
10
12
DRIVER
21
DRIVER
23
27
DRIVER
25
6
8
DRIVER
16
TFDR
PSB
XRST
SLED/SPINDLE MOTOR DRIVE
FOCUS/TRACKING COIL DRIVE
IC152
09
M
M
M102
SLED MOTOR
M101
SPINDLE MOTOR
DETECTOR
F
I
J
C
D
B
A
E
VC
LD
PD
ILCC
15
14
ATRAC
ENCODER/
DECODER
SAMPLING
RATE
CONVERTER
DTRF
CKRF
XLRF
FOCNT
79
82
81
80
93
94
95
10
SPRD
SPFD
FG IN
XRST
SPINDLE
SERVO
ADIP
DEMODULATOR/
DECODER
78
ADFG
A/D
CONVERTER
SERVO
DSP
APC
PWM
GENERATOR
21
26
25
20
SUBCODE
PROCESSOR
11
12
MONITOR
CONTROL
4
3
2
1
3
CPU
I/F
AUTO
SEQUENCER
16
27
28
7
5
6
8
9
7
3
512FS
M
M103
LOADING MOTOR
BCK
LRCK
BUFFER IC123
DRAM
IC124
SQSY
DQSY
MNT3
MNT2
MNT1
MNT0
SENS
SRDT
SCLK
SWDT
XLAT
DIN1
19
DIN0
ADDT
DADT
DOUT
91
92
85
86
89
88
83
13
RECP
APCREF
FFDR
FRDR
TFDR
TRDR
SFDR
SRDR
FOCNT
XLAT
SCLK
SWDT
CSLED
SE
TE
26
28
32
30
ADFG
ADIN
ADFM
29
31
34
66
68
75
74
FE
VC
TE
SE
33
67
36
37
35
64
63
65
AUX
BOTM
PEAK
ABCD
FE
AUX1
BOTM
PEAK
ABCD
38
RF
57
RFI
59
60
61
62
ABCD
AMP
FOCUS
ERROR
AMP
I
J
A
B
C
D
E
F
VC
CVB
TEMP
AMP
TEMPR
TEMPI
APC
APCREF
EQADJ
3TADJ
WBLADJ
TRACKING
ERROR
AMP
OPTICAL PICK-UP BLOCK
(KMS-260B/S1NP)
48 47 46 40
RF AMP
IC101
EFMO
TX
XINIT
CLOCK
GENERATOR
14
15
18
19
29
30
3
4
SPFD
SPRD
SFDR
SRDR
TRDR
FRDR
FFDR
OVER WRITE HEAD DRIVE
IC181
OSCI
XBCK
LRCK
VC
VC
PEAK
&
BOTTOM
TRK–
TRK+
FSC+
FSC–
SLED+
SLED–
SPDL+
SPDL–
DIGITAL SERVO SIGNAL PROCESSOR, DIGITAL SIGNAL PROCESSOR
EFM/ACIRC ENCODER/DECODER, SHOCK-PROOF MEMORY CONTROLLER,
ATRAC ENCODER/DECODER
IC121
D-IN.0
D-IN.1
ADDT
DADT
D-OUT
SQSY
DQSY
SCTX
XINT
MNT3
MNT2
MNT1
MNT0
SENS
SRDT
SCLK
SWDT
XLAT CH
LDON
DIG RST
WRPWR
MOD
6
5
SDA
SDA
SCL
SCL
LIMIT-IN
REFLECT
PROTECT
CHACK-IN
PACK-OUT
PLAY-P
REC-P
EEP ROM
IC171
LOAD-IN
LOAD-OUT
DETECT SW
S101, S102,
S601-604
100
49 • 48 • 50 • 51
34   31 • 36   40 • 45
D0
D3
A00
A09
47
46
3
4
17
16
1
2
18
19
6
9
11
15
5
XWE
XRAS
XCAS
XOE
DQ1
DQ4
A0
A9
44
43
20
XWE
XRAS
XCAS
XOE
SHOCK
RESISTANT
MEMORY
CONTROLLER
8
11
10
13
9
12
4
5
DIGITAL
AUDIO
I/F
MAIN
SECTION
(Page 33)
MAIN
SECTION
(Page 33)
MAIN
SECTION
(Page 33)
• R-ch is omitted.
• Signal path
: PB
: REC
: PB (Digital)
: REC (Digital)
A
B
C
6-1. BLOCK DIAGRAMS
– BD SECTION –
Page of 57
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