Sony MDS-S9 Service Manual ▷ View online
MDS-S9
46
46
•
BD BOARD IC101 CXA2523AR (RF AMP, FOCUS/TRACKING ERROR AMP)
Pin No.
Pin Name
I/O
Description
1
I
I
I-V converted RF signal I input from the optical pick-up block detector
2
J
I
I-V converted RF signal J input from the optical pick-up block detector
3
VC
O
Middle point voltage (+1.65V) generation output terminal
4 to 9
A to F
I
Signal input from the optical pick-up detector
10
PD
I
Light amount monitor input from the optical pick-up block laser diode
11
APC
O
Laser amplifier output to the automatic power control circuit
12
APCREF
I
Reference voltage input for setting laser power from the CXD2662R (IC151)
13
GND
—
Ground terminal
14
TEMPI
I
Connected to the temperature sensor
15
TEMPR
O
Output terminal for a temperature sensor reference voltage
16
SWDT
I
Writing serial data input from the CXD2662R (IC151)
17
SCLK
I
Serial data transfer clock signal input from the CXD2662R (IC151)
18
XLAT
I
Serial data latch pulse signal input from the CXD2662R (IC151)
19
XSTBY
I
Standby control signal input terminal “L”: standby (fixed at “H” in this set)
20
F0CNT
I
Center frequency control voltage input terminal of internal circuit (BPF22, BPF3T, EQ) input
from the CXD2662R (IC151)
from the CXD2662R (IC151)
21
VREF
O
Reference voltage output terminal Not used (open)
22
EQADJ
I
Center frequency setting terminal for the internal circuit (EQ)
23
3TADJ
I
Center frequency setting terminal for the internal circuit (BPF3T)
24
VCC
—
Power supply terminal (+3.3V)
25
WBLADJ
I
Center frequency setting terminal for the internal circuit (BPF22)
26
TE
O
Tracking error signal output to the CXD2662R (IC151)
27
CSLED
I
Connected to the external capacitor for low-pass filter of the sled error signal
28
SE
O
Sled error signal output to the CXD2662R (IC151)
29
ADFM
O
FM signal output of the ADIP
30
ADIN
I
Receives a ADIP FM signal in AC coupling
31
ADAGC
I
Connected to the external capacitor for ADIP AGC
32
ADFG
O
ADIP duplex signal (22.05 kHz
±
1 kHz) output to the CXD2662R (IC151)
33
AUX
O
Auxiliary signal (I
3
signal/temperature signal) output to the CXD2662R (IC151)
34
FE
O
Focus error signal output to the CXD2662R (IC151)
35
ABCD
O
Light amount signal (ABCD) output to the CXD2662R (IC151)
36
BOTM
O
Light amount signal (RF/ABCD) bottom hold output to the CXD2662R (IC151)
37
PEAK
O
Light amount signal (RF/ABCD) peak hold output to the CXD2662R (IC151)
38
RF
O
Playback EFM RF signal output to the CXD2662R (IC151)
39
RFAGC
I
Connected to the external capacitor for RF auto gain control circuit
40
AGCI
I
Receives a RF signal in AC coupling
41
COMPO
O
User comparator output terminal Not used (open)
42
COMPP
I
User comparator input terminal Not used (fixed at “L”)
43
ADDC
I
Connected to the external capacitor for cutting the low band of the ADIP amplifier
44
OPO
O
User operational amplifier output terminal Not used (open)
45
OPN
I
User operational amplifier inversion input terminal Not used (fixed at “L”)
46
RFO
O
RF signal output
47
MORFI
I
Receives a MO RF signal in AC coupling
48
MORFO
O
MO RF signal output
6-15.
IC PIN FUNCTION DESCRIPTION
•
BD BOARD IC151 CXD2662R
Pin No.
Pin Name
I/O
Description
1
MNT0 (FOK)
O
Focus OK signal output terminal “H” is output when focus is on (“L”: NG)
Not used (open)
Not used (open)
2
MNT1 (SHOCK)
O
Track jump detection signal output to the system controller (IC1)
3
MNT2 (XBUSY)
O
Busy monitor signal output to the system controller (IC1)
4
MNT3 (SLOCK)
O
Spindle servo lock status monitor signal output terminal Not used (open)
5
SWDT
I
Writing serial data signal input from the system controller (IC1)
6
SCLK
I (S)
Serial data transfer clock signal input from the system controller (IC1)
7
XLAT
I (S)
Serial data latch pulse signal input from the system controller (IC1)
8
SRDT
O (3)
Reading serial data signal output to the system controller (IC1)
9
SENS
O (3)
Internal status (SENSE) output to the system controller (IC1)
10
XRST
I (S)
Reset signal input from the system controller (IC1) “L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the system controller (IC1)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output to the system controller (IC1)
“L” is output every 13.3 msec Almost all, “H” is output
“L” is output every 13.3 msec Almost all, “H” is output
13
RECP
I
Laser power selection signal input from the system controller (IC1)
“L”: playback mode, “H”: recording mode
“L”: playback mode, “H”: recording mode
14
XINT
O
Interrupt status output to the system controller (IC1)
15
TX
O
Magnetic head on/off signal output to the over write head drive (IC181)
16
OSCI
I
System clock signal (512Fs=22.5792 MHz) input from the oscillator circuit
17
OSCO
O
System clock signal (512Fs=22.5792 MHz) output terminal Not used (open)
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 22.5792 MHz, “H”: 45.1584 MHz (fixed at “L” in this set)
“L”: 22.5792 MHz, “H”: 45.1584 MHz (fixed at “L” in this set)
19
DIN0
I
Digital audio signal input terminal when recording mode (for digital optical input)
20
DIN1
I
Digital audio signal input terminal when recording mode (for digital optical input) Not used
21
DOUT
O
Digital audio signal output terminal when playback mode (for digital optical output) Not used
22
DADTAI
I
Serial data input from the system controller (IC1)
23
LRCKI
I
L/R sampling clock signal (44.1 kHz) input from the system controller (IC1)
24
XBCKI
I
Bit clock signal (2.8224 MHz) input from the system controller (IC1)
25
ADDT
I
Recording data input from the A/D, D/A converter (IC500)
26
DADT
O
Playback data output to the A/D, D/A converter (IC500)
27
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC500)
28
XBCK
O
Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC500)
29
FS256
O
Clock signal (11.2896 MHz) output terminal Not used (open)
30
DVDD
—
Power supply terminal (+3.3V) (digital system)
31 to 34
A03 to A00
O
Address signal output to the D-RAM (IC153)
35
A10
O
Address signal output to the external D-RAM Not used (open)
36 to 40
A04 to A08
O
Address signal output to the D-RAM (IC153)
41
A11
O
Address signal output to the external D-RAM Not used (open)
42
DVSS
—
Ground terminal (digital system)
43
XOE
O
Output enable signal output to the D-RAM (IC153) “L” active
44
XCAS
O
Column address strobe signal output to the D-RAM (IC153) “L” active
45
A09
O
Address signal output to the D-RAM (IC153)
46
XRAS
O
Row address strobe signal output to the D-RAM (IC153) “L” active
47
XWE
O
Write enable signal output to the D-RAM (IC153) “L” active
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO SIGNAL PROCESSOR, EFM/ACIRC ENCODER/DECODER,
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
47
MDS-S9
Pin No.
Pin Name
I/O
Description
48
D1
I/O
49
D0
I/O
50
D2
I/O
51
D3
I/O
52
MVCI
I (S)
Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
53
ASYO
O
Playback EFM full-swing output terminal
54
ASYI
I (A)
Playback EFM asymmetry comparator voltage input terminal
55
AVDD
—
Power supply terminal (+3.3V) (analog system)
56
BIAS
I (A)
Playback EFM asymmetry circuit constant current input terminal
57
RFI
I (A)
Playback EFM RF signal input from the CXA2523AR (IC101)
58
AVSS
—
Ground terminal (analog system)
59
PCO
O (3)
Phase comparison output for master clock of the recording/playback EFM master PLL
60
FILI
I (A)
Filter input for master clock of the recording/playback master PLL
61
FILO
O (A)
Filter output for master clock of the recording/playback master PLL
62
CLTV
I (A)
Internal VCO control voltage input of the recording/playback master PLL
63
PEAK
I (A)
Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC101)
64
BOTM
I (A)
Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC101)
65
ABCD
I (A)
Light amount signal (ABCD) input from the CXA2523AR (IC101)
66
FE
I (A)
Focus error signal input from the CXA2523AR (IC101)
67
AUX1
I (A)
Auxiliary signal (I
3
signal/temperature signal) input from the CXA2523AR (IC101)
68
VC
I (A)
Middle point voltage (+1.65V) input from the CXA2523AR (IC101)
69
ADIO
O (A)
Monitor output of the A/D converter input signal Not used (open)
70
AVDD
—
Power supply terminal (+3.3V) (analog system)
71
ADRT
I (A)
A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
72
ADRB
I (A)
A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
73
AVSS
—
Ground terminal (analog system)
74
SE
I (A)
Sled error signal input from the CXA2523AR (IC101)
75
TE
I (A)
Tracking error signal input from the CXA2523AR (IC101)
76
DCHG
I (A)
Connected to the +3.3V power supply
77
TEST4
I
Input terminal for the test Not used (fixed at “H”)
78
ADFG
I (S)
ADIP duplex FM signal (22.05 kHz
±
1 kHz) input from the CXA2523AR (IC101)
79
F0CNT
O
Filter f0 control signal output to the CXA2523AR (IC101)
80
XLRF
O
Serial data latch pulse signal output to the CXA2523AR (IC101)
81
CKRF
O
Serial data transfer clock signal output to the CXA2523AR (IC101)
82
DTRF
O
Writing serial data output to the CXA2523AR (IC101)
83
APCREF
O
Control signal output to the reference voltage generator circuit for the laser automatic power
control
control
84
TEST0
O
Input terminal for the test Not used (open)
85
TRDR
O
Tracking servo drive PWM signal (–) output to the BH6519FS (IC141)
86
TFDR
O
Tracking servo drive PWM signal (+) output to the BH6519FS (IC141)
87
DVDD
—
Power supply terminal (+3.3V) (digital system)
88
FFDR
O
Focus servo drive PWM signal (+) output to the BH6519FS (IC141)
89
FRDR
O
Focus servo drive PWM signal (–) output to the BH6519FS (IC141)
90
FS4
O
Clock signal (176.4 kHz) output terminal (X’tal system) Not used (open)
91
SRDR
O
Sled servo drive PWM signal (–) output to the BH6519FS (IC141)
92
SFDR
O
Sled servo drive PWM signal (+) output to the BH6519FS (IC141)
93
SPRD
O
Spindle servo drive PWM signal (–) output to the BH6519FS (IC141)
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
Two-way data bus with the D-RAM (IC153)
48
MDS-S9
Pin No.
Pin Name
I/O
Description
94
SPFD
O
Spindle servo drive PWM signal (+) output to the BH6519FS (IC141)
95
FGIN
I (S)
96
TEST1
I
97
TEST2
I
98
TEST3
I
99
DVSS
—
Ground terminal (digital system)
100
EFMO
O
EFM signal output terminal when recording mode
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
Input terminal for the test (fixed at “L”)
49
MDS-S9
•
MAIN BOARD IC1 M30805MG-216GP (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
FL-DATA
O
Serial data output to the fluorescent indicator tube/LED driver (IC761)
2
FL-CLK
O
Serial data transfer clock signal output to the fluorescent indicator tube/LED driver (IC761)
3
A1 IN
I
Sircs remote control signal input terminal of the CONTROL A1II Not used (fixed at “H”)
4
RMC
I
Remote control signal input from the remote control receiver (IC781)
5 to 7
NC
O
Not used (open)
8
MUTE
O
Audio line muting on/off control signal output “L”: line muting on, “H”: line muting off
9
RESET
O
Reset signal output to the A/D, D/A converter (IC500) “L”: reset
10
LATCH
O
Serial data latch pulse signal output to the A/D, D/A converter (IC500)
11
LD-LOW
O
Loading motor drive voltage control signal output for the loading motor driver (IC440)
“H” active
“H” active
12
LDIN
O
Motor control signal output to the loading motor driver (IC440) “L” active *1
13
LDOUT
O
Motor control signal output to the loading motor driver (IC440) “L” active *1
Laser modulation selection signal output to the HF module switch circuit
Stop: “L”, Playback power: “H”,
Recording power:
14
MOD
O
15
BYTE
I
External data bus line byte selection signal input “L”: 16 bit, “H”: 8 bit (fixed at “L”)
16
CNVSS
—
Ground terminal
17
XCIN
I
Sub system clock input terminal (32.768 kHz) Not used (open)
18
XCOUT
O
Sub system clock output terminal (32.768 kHz) Not used (open)
19
RESET
I
System reset signal input from the regulator (IC400) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
20
XOUT
O
Main system clock output terminal (10 MHz)
21
VSS
—
Ground terminal
22
XIN
I
Main system clock input terminal (10 MHz)
23
VCC
—
Power supply terminal (+3.3V)
24
NMI
I
Non-maskable interrupt input terminal “L” active (fixed at “H” in this set)
25
DQSY
I
Digital In U-bit CD format subcode Q sync (SCOR) input from the CXD2662R (IC151)
“L” is input every 13.3 msec Almost all, “H” is input
“L” is input every 13.3 msec Almost all, “H” is input
26
PDOWN
I
Power down detection signal input from the regulator (IC400)
“L”: power down, normally: “H”
“L”: power down, normally: “H”
27
SQSY
I
Subcode Q sync (SCOR) input from the CXD2662R (IC151)
“L” is input every 13.3 msec Almost all, “H” is input
“L” is input every 13.3 msec Almost all, “H” is input
28
KEYBD-CLK
I
Serial data transfer clock signal input from the key board Not used (fixed at “H”)
29
LDON
O
Laser diode on/off control signal output to the automatic power control circuit “H”: laser on
30
LIMIT-IN
I
Detection signal input from the sled limit-in detect switch (S101)
The optical pick-up is inner position when “L”
The optical pick-up is inner position when “L”
31
A1 OUT
O
Sircs remote control signal output terminal of the CONTROL A1II Not used (open)
2 sec
0.5 sec
*1 Loading motor (M103) control
LOADING
EJECT
BRAKE
STOP
LDIN (pin qs)
“L”
“H”
“L”
“H”
LDOUT (pin qd)
“H”
“L”
“L”
“H”
Terminal
Mode
Click on the first or last page to see other MDS-S9 service manuals if exist.