Sony MDS-PC2 Service Manual ▷ View online
45
100 99 98 97 96 95
94 93
EFMO
DVSS
TEST3
TEST2
TEST1
TEST0
SPFD
SPRD
92
SFDR
91
SRDR
90
FS4
89
FRDR
88
FFDR
87
DVDD
86
TFDR
85
TRDR
84
LDDR
83
APCREF
82
DTRF
81
CKRF
80
XLRF
79
F0CNT
78
ADFG
77
APC
76
DCHG
75 TE
74 SE
73 AVSS
72 ADRB
71 ADRT
70 AVDD
69 ADIO
62 CLTV
61 FILO
60 FILI
59 PCO
57 RFI
58 AVSS
56 BIAS
55 AVDD
54 ASYI
53 ASYO
52 MVCI
51 D3
68 VC
67 AUX1
66 FE
65 ABCD
64 BOTM
63 PEAK
50
D2
49
D0
48
D1
47
XWE
46
XRAS
45
A09
44
XCAS
43
XOE
42
DVSS
41
A11
40
A08
39
A07
38
A06
37
A05
36
A04
35
A10
34
A00
33
A01
32
A02
31
A03
30
DVDD
28
XBCK
29
FS256
26
DADT
27
LRCK
24
XBCKI
25
ADDT
23
LRCKI
22
DATAI
21
DOUT
20
DIN1
19
DIN0
18
XTSL
17
OSCO
16
OSCI
15
TX
14
XINT
13
RECP
12
DQSY
11
SQSY
10
XRST
9
SENS
8
SRDT
7
XLAT
6
SCLK
5
SWDT
4
MNT3
3
MNT2
2
MNT1
1
MNT0
PWM
GENERATOR
AUTO
SEQUENCER
SERVO
DSP
CPU I/F
MONITOR
CONTROL
CONTROL
SPINDLE
SERVO
EACH
BLOCK
BLOCK
EACH
BLOCK
BLOCK
DIGITAL
AUDIO
I/F
SAMPLING
RATE
CONVERTER
CLOCK
GENERATOR
SUBCODE
PROCESSOR
EACH
BLOCK
BLOCK
A/D
CONVERTER
ANALOG
MUX
EFM/ACIRC
ENCODER/
DECODER
APC
PLL
SHOCK RESISTANT
MEMORY CONTROLLER
ATRAC
ENCODER/DECODER
DRAM
ADIP
DEMODULATOR/
DECODER
COMP
ADDRESS/DATA BUS A00 - A11, D0 - D3
IC121 CXD2654R
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
VG
IN4R
IN4F
VM4
OUT4F
PGND4
OUT4R
VM34
OUT3R
PGND3
OUT3F
VM3
IN3F
IN3R
PSB
CAPA–
CAPA+
IN2R
IN2F
VM2
OUT2F
PGND2
OUT2R
VM12
OUT1R
PGND1
OUT1F
VM1
IN1F
IN1R
V
DD
CHARGE
PUMP.
OSC
INTERFACE
AMP
INTERFACE
AMP
AMP
INTERFACE
PREDRIVE
PREDRIVE
PREDRIVE
PREDRIVE
AMP
INTERFACE
AMP
AMP
AMP
V
DD
PSB
AMP
IC152 BH6511FS-E2
46
• MAIN section
3
4
5
6
2
8
7
1
VADCN
VADCP
VINL2
PGA
PGA
0DB/6DB
SWITCH
NOISE SHAPER
INTERPOLATION FILTER
DSP FEATURES
PRAK
DETECTOR
L3-BUS
INTERFACE
DECIMATION FILTER
DIGITAL
INTERFACE
DIGITAL MIXER
DIGITAL AGC
ADC1L
ADC2L
ADC2R
ADC1R
DAC
DAC
0DB/6DB
SWITCH
VSS(AD)
VDD(AD)
VINL1
VDDD
VSSD
18
16
19
17
26
25
27
24
13
15
14
9
22
10
11
23
28
12
20
21
DATAO
BCK
WS
DATAI
QMUTE
VREF
VOUTL
V
DD(DAC)
VSS(DAC)
VOUTR
TEST2
TEST1
SYSCLK
L3DATA
L3MODE
L3CLOCK
OVERFLOW
AGCSTAT
VINR1
VINR2
IC301 UDA1341TS/N2
1
LOGIC
PREDRIVER
VREF
2
3
4
5
10
9
8
7
6
IN2
IN1
VM
VREF
VCONT
VCC
OUT2
GND
OUT1 VS
IC441 LB1830M
47
6-16. IC PIN FUNCTIONS
• IC101 RF Amplifier (CXA2523AR) (BD board)
Pin No.
Pin Name
I/O
Function
I
J
VC
A to F
PD
APC
APCREF
GND
TEMPI
TEMPR
SWDT
SCLK
XLAT
XSTBY
F0CNT
VREF
EQADJ
3TADJ
Vcc
WBLADJ
TE
CSLED
SE
ADFM
ADIN
ADAGC
ADFG
AUX
FE
ABCD
BOTM
PEAK
RF
RFAGC
AGCI
COMPO
COMPP
ADDC
OPO
OPN
RFO
MORFI
MORFO
I
I
O
I
I
O
I
—
I
O
I
I
I
I
I
O
I/O
I/O
—
I/O
O
—
O
O
I
—
O
O
O
O
O
O
O
—
I
O
I
I/O
O
I
O
I
O
I-V converted RF signal I input
I-V converted RF signal J input
Middle point voltage (+1.5V) generation output
Signal input from the optical pick-up detector
Light amount monitor input
Laser APC output
Reference voltage input for setting laser power
Ground
Temperature sensor connection
Reference voltage output for the temperature sensor
Serial data input from the CXD2650R or CXD2652AR
Serial clock input from the CXD2650R or CXD2652AR
Latch signal input from the CXD2650R or CXD2652AR
“L”: Latch
Stand by signal input
“L”: Stand by
Center frequency control voltage input of BPF22, BPF3T, EQ from the CXD2650R or
CXD2652AR
Reference voltage output (Not used)
Center frequency setting pin for the internal circuit EQ
Center frequency setting pin for the internal circuit BPF3T
+3V power supply
Center frequency setting pin for the internal circuit BPF22
Tracking error signal output to the CXD2650R or CXD2652AR
External capacitor connection pin for the sled error signal LPF
Sled error signal output to the CXD2650R or CXD2652AR
FM signal output of ADIP
ADIP signal comparator input
ADFM is connected with AC coupling
External capacitor connection pin for AGC of ADIP
ADIP duplex signal output to the CXD2650R or CXD2652AR
I
3
signal/temperature signal output to the CXD2650R or CXD2652AR
(Switching with a serial command)
Focus error signal output to the CXD2650R or CXD2652AR
Light amount signal output to the CXD2650R or CXD2652AR
RF/ABCD bottom hold signal output to the CXD2650R or CXD2652AR
RF/ABCD peak hold signal output to the CXD2650R or CXD2652AR
RF equalizer output to the CXD2650R or CXD2652AR
External capacitor connection pin for the RF AGC circuit
Input to the RF AGC circuit
The RF amplifier output is input with AC coupling
User comparator output (Not used)
User comparator input (Fixed at “L”)
External capacitor pin for cutting the low band of the ADIP amplifier
User operation amplifier output (Not used)
User operation amplifier inversion input (Fixed at “L”)
RF amplifier output
Groove RF signal is input with AC coupling
Groove RF signal output
1
2
3
4 to 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
• Abbreviation
APC: Auto Power Control
AGC: Auto Gain Control
AGC: Auto Gain Control
48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 to 34
35
36 to 40
41
42
43
44
45
46
47
• IC121 Digital Signal Processor, Digital Servo Signal Processor, EFM/ACIRC Encoder/Decoder,
Shock-proof Memory Controller, ATRAC Encoder/Decoder, 2M Bit DRAM (CXD2654R) (BD board)
Function
Pin No.
Pin Name
I/O
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DIN0
DIN1
DOUT
DADTI
LRCKI
XBCKI
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
I
I
O
I
I
I
O
I
I
I
I
O
O
O
O
—
O
O
O
O
—
O
O
O
O
O
FOK signal output to the system control (monitor output)
“H” is output when focus is on
Track jump detection signal output to the system control (monitor output)
Monitor 2 output to the system control (monitor output)
Monitor 3 output to the system control (monitor output)
Writing data signal input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Reading data signal output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control
“L”: Reset
Subcode Q sync (SCOR) output to the system control
“L” is output every 13.3 msec. Almost all, “H” is output
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system
control
Laser power switching input from the system control
“H”: Recording, “L”: Playback
Interrupt status output to the system control
Recording data output enable input from the system control
System clock input (512Fs=22.5792 MHz)
System clock output (512Fs=22.5792 MHz) (Not used)
System clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (Fixed at “H”)
Digital audio input (Optical input)
Digital audio input (Optical input)
Digital audio output (Optical output)
Serial data input
LR clock input
“H” : Lch, “L” : R ch
Serial data clock input
Data input from the A/D converter
Data output to the D/A converter
LR clock output for the A/D and D/A converter (44.1 kHz)
Bit clock output to the A/D and D/A converter (2.8224 MHz)
11.2896 MHz clock output (Not used)
+3V power supply (Digital)
DRAM address output
DRAM address output (Not used)
DRAM address output
DRAM address output (Not used)
Ground (Digital)
Output enable output for DRAM
CAS signal output for DRAM
Address output for DRAM
RAS signal output for DRAM
Write enable signal output for DRAM (Used : CXD2652AR, Not used : CXD2650R)
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
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