Sony MDS-JE780 Service Manual ▷ View online
MDS-JE780
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• IC201 CXD2664R Digital Signal Processor, Digital Servo Signal Processor (BD BOARD)
Description
Pin No.
Pin Name
I/O
Not used (open)
Track jump detection signal output to the system control
In the state of executire command signal output
Not used (open)
Power supply
Serial data input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Ground
Serial reading data output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control
“L”: Reset
Subcode Q sync (SCOR) output to the system control
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system
control
Laser power switching input from the system control
“H”: Recording, “L”: Playback
Interrupt status output to the system control
Recording data output enable input from the system control
Power supply
System clock input (Fixed at “L”)
System clock input (Input terminal during OSCN:“H” )
Internal oscillating circuit control signal input
Ground
System clock frequency setting
(Fixed at “H”)
Digital audio input (Optical input)
Digital audio input (USB input)
Digital audio output (Optical output)
Serial data input
LR clock input
Serial data bit clock input
Power supply
Ground
Data input from the A/D converter
Data output to the D/A converter
LR clock output for the A/D and D/A converter
Bit clock output to the A/D and D/A converter
256Fs clock output (Not used)
Write enable signal output for DRAM
Read enable output for DRAM
Power supply
Ground
DRAM address output (Not used) (Open)
Data input/output for DRAM
* O (3) for 3-state output in the column I/O
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
VDC0
SWDT
SCLK
XLAT
VSC0
SRDT
SENS
XRST
SQSY
DQSY
RPWR
XINT
TX
VDIO0
OSCI
OSCO
OSCN
VSIO0
XTSL
DIN0
DIN1
DOUT
DADTI
LRCKI
XBCKI
VDC1
VSC1
ADDT
DADT
LRCK
XBCK
FS256
XWE
XOE
DRVDD0
DRVSS0
A11
D3
D0
D2
D1
O
O
O
O
—
I
I
I
—
O (3)
O (3)
I
O
O
I
O
O
—
I
I/O
I
—
I
I
I
O
I
I
I
—
—
I
O
O
O
O
O
O
—
—
O
I/O
I/O
I/O
I/O
6-13. IC PIN FUNCTION DESCRIPTION
• IC101 CXA2523AR RF Amplifier (BD BOARD)
Pin No.
Pin Name
I/O
Description
I
J
VC
A to F
PD
APC
APCREF
GND
TEMPI
TEMPR
SWDT
SCLK
XLAT
XSTBY
F0CNT
VREF
EQADJ
3TADJ
Vcc
WBLADJ
TE
CSLED
SE
ADFM
ADIN
ADAGC
ADFG
AUX
FE
ABCD
BOTM
PEAK
RF
RFAGC
AGCI
COMPO
COMPP
ADDC
OPO
OPN
RFO
MORFI
MORFO
I
I
O
I
I
O
I
—
I
O
I
I
I
I
I
O
I
I
—
I
O
—
O
O
I
—
O
O
O
O
O
O
O
—
I
O
I
—
O
I
O
I
O
I-V converted RF signal I input
I-V converted RF signal J input
Middle point voltage generation output
Signal input from the optical pick-up detector
Light amount monitor input
Laser APC output
Reference voltage input for setting laser power
Ground
Temperature sensor connection
Reference voltage output for the temperature sensor
Serial data input from the CXD2664R
Serial clock input from the CXD2664R
Latch signal input from the CXD2664R
“L”: Latch
Stand by signal input
(Fixed at “H”)
Center frequency control voltage input of BPF22, BPF3T, EQ from the CXD2664R
Reference voltage output (Not used)
Center frequency setting pin for the internal circuit EQ
Center frequency setting pin for the internal circuit BPF3T
Power supply
Center frequency setting pin for the internal circuit BPF22
Tracking error signal output to the CXD2664R
External capacitor connection pin for the sled error signal LPF
Sled error signal output to the CXD2664R
FM signal output of ADIP
ADIP signal comparator input
ADFM is connected with AC coupling
External capacitor connection pin for AGC of ADIP
ADIP duplex signal output to the CXD2664R
I
3
signal/temperature signal output to the CXD2664R
Focus error signal output to the CXD2664R
Light amount signal output to the CXD2664R
RF/ABCD bottom hold signal output to the CXD2664R
RF/ABCD peak hold signal output to the CXD2664R
RF equalizer output to the CXD2664R
External capacitor connection pin for the RF AGC circuit
The RF amplifier output is input with AC coupling
User comparator output (Not used)
User comparator input (Fixed at “L”)
External capacitor pin for cutting the low band of the ADIP amplifier
User operation amplifier output (Not used)
User operation amplifier inversion input (Fixed at “L”)
RF amplifier output
Groove RF signal is input with AC coupling
Groove RF signal output
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4 - 9
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• Abbreviation
APC: Auto Power Control
AGC: Auto Gain Control
AGC: Auto Gain Control
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MDS-JE780
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Description
Pin No.
Pin Name
I/O
XCAS
XRAS
A09
A08
A10
A07
A00
A06
A01
A05
A02
VDC2
VSC2
A04
A03
DRVDD1
DRVSS1
TEST0
TEST1
TEST2
AVD1
ASYO
ASYI
BIAS
RFI
AVS1
PCO
FILI
FILO
CLTV
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
ADRT
ADRB
SE
TE
AVD2
AVS2
DCHG
APC
ADFG
CAS signal output for DRAM
RAS signal output for DRAM
DRAM address output
Not used (Open)
DRAM address output
Power supply
Ground
DRAM address output
DRAM address output
Power supply
Ground
Not used (Fixed at “L”)
Not used (Fixed at “H”)
Not used (Open)
Power supply
Play back EFM duplex signal output
Play back EFM comparator slice level input
Play back EFM comparator bias current input
Play back EFM RF signal input
Ground
Phase comparison output for the recording/playback EFM master PLL
Filter input for the recording/playback EFM master PLL
Filter output for the recording/playback EFM master PLL
Internal VCO control voltage input for the recording/playback EFM master PLL
Light amount signal peak hold input
Light amount signal bottom hold input
Light amount signal input
Focus error signal input from the CXA2523AR
Auxiliary A/D input
Middle point voltage input from the CXA2523AR
Monitor output of the A/D converter input signal (Not used) (Open)
A/D converter operational range upper limit voltage input (Fixed at “H”)
A/D converter operational range lower limit voltage input (Fixed at “L”)
Sled error signal input from the CXA2523AR
Tracking error signal input from the CXA2523AR
Power supply
Ground
Connected to +3V power supply
APC error signal input (Not used) (Fixed at “H”)
ADIP duplex FM signal input from the CXA2523AR
O
O
O
O
O
O
O
O
O
O
O
—
—
O
O
—
—
I
I
I
—
O
I (A)
I (A)
I (A)
—
O (3)
I (A)
O (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
I (A)
I (A)
I (A)
I (A)
—
—
I (A)
I
I
• Abbreviation
EFM: Eight to Fourteen Modulation
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
* I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
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MDS-JE780
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111
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Description
Pin No.
Pin Name
I/O
VDIO1
VSIO1
F0CNT
VDC3
VSC3
XLRF
CLRF
DTRF
APCR
LDDR
TRDR
TFDR
FFDR
FRDR
FS4
SRDR
SFDR
SPRD
SPFD
FGIN
TST1 to TST3
EFMO
VDIO2
VSIO2
VDC4
VSC4
MDDT1
—
—
O
—
—
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
O
—
—
—
—
I
Power supply
Ground
Filter f0 control output to the CXA2523AR
Power supply
Ground
Control latch output to the CXA2523AR
Control clock output to the CXA2523AR
Control data output to the CXA2523AR
Reference PWM output for the laser APC
PWM output for the laser digital APC (Not used) (Open)
Tracking servo drive PWM output (–)
Tracking servo drive PWM output (+)
Focus servo drive PWM output (+)
Focus servo drive PWM output (–)
4Fs clock signal output (Not used) (Open)
Sled servo drive PWM output (–)
Sled servo drive PWM output (+)
Spindle servo drive PWM output (–)
Spindle servo drive PWM output (+)
Spindle CAV servo FG signal input (Fixed at “L”)
Test input (Fixed at “L”)
EFM output when recording
Power supply
Ground
Power supply
Ground
MD data mode1 switching signal input (Fixed at “L”)
• Abbreviation
EFM: Eight to Fourteen Modulation
49
MDS-JE780
1
FLDT
O
Serial data output to the display driver
2
FLCK
O
Serial clock signal output to the display driver. L: Active
3
A1-IN
I
A1 Control input (Not used) (Open)
4
SIRCS
I
Remote control input
5
NETMD_SO
O
Serial data output to UNICORN NETMD-USB I/F
6
NETMD_SI
I
Serial data input from UNICORN NETMD-USB I/F
7
NETMD_CLK
O
Clock signal output to UNICORN NETMD-USB I/F
8
BYTE
I
Data bus changed input (Fixed at “L”)
9
CNVSS
—
Ground
10
XIN-T
I
Not used (Fixed at “L”)
11
XOUT-T
O
Not used (Open)
12
S.RST
I
System rest input
13
XOUT
O
Main clock output (10MHz)
14
GND
—
Ground
15
XIN
I
Main clock input (10MHz)
16
VCC
—
Power supply
17
NMI
I
Fixed at H (Fixed at “H”)
18
DQSY
I
Digital in sync input (Record system)
19
P.DOWN
I
Power down detection input L: Power down
20
SQSY
I
ADIP (MO) sync or subcode Q (PIT) sync input from CXD2664R (Playback system)
21
KB.CLK
I
Keyboard clock input
22
KB.DATA
I
Keyboard data input
23
IIC BUSY
I
IIC cable connect check (Not used) (Open)
24
A1 OUT
O
A1 control output (Not used) (Open)
25
XINIT
I
Interrupt status input from CXD2664R
26
*BEEP
O
Not used (Open)
27
LRCKI
O
Not used (Open)
28
IIC POWER
O
Not used (Open)
29
IIC CLK
O
Not used (Fixed at “L”)
30
IIC DATA
I/O
Not used (Fixed at “L”)
31
SWDT
O
Writing data signal output to the serial bus
32
SRDT
I
Reading data signal input from the serial bus
33
SCLK
O
Clock signal output to the serial bus
34
KB.CLK-CTRL
O
Keyboard clock ON/OFF signal output
35
CLIP-TX
O
Not used (Open)
36
CLIP-RX
I
Not used (Open)
37
XBCK1
O
Not used (Open)
38
MUTE
O
Line out muting output
39
ADA.RESET
O
Reset signal output to the AK4524
40
ADA. LATCH
O
Latch signal output to the AK4524
41
EPN
I
Not used (Fixed at “L”)
42
L : DINT1/H : CLIP
O
Not used (Open)
43
NC
O
Not used (Open)
44
PROTECT
I
Recording-protection claw detection input from the protection detection switch H: Protect
45
SCL
O
Clock signal output to the EEP-ROM
46
CE
I
Not used (Pull-up)
Description
Pin Name
Pin No.
I/O
• IC1 M30833FJFP-JE7-1 SYSTEM CONTROL (MAIN BOARD)
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