Sony MDS-JA555ES Service Manual ▷ View online
65
Pin No.
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
O
—
O
O
O
O
O
O
O
I (S)
I
I
I
—
O
Description
Tracking servo drive PWM signal output to BH6511FS (IC152)
Power supply (+3.3 V) (Digital)
Focus servo drive PWM signal output to BH6511FS (IC152) (+)
Focus servo drive PWM signal output to BH6511FS (IC152) (-)
176.4 kHz clock signal output (X’tal system) Not used in this system (Blank terminal)
Sled servo drive PWM signal output to BH6511FS (IC152) (-)
Sled servo drive PWM signal output to BH6511FS (IC152) (+)
Spindle servo drive PWM signal output to BH6511FS (IC152) (-)
Spindle servo drive PWM signal output to BH6511FS (IC152) (+)
Input pin for test (Fixed at “L”)
Input pin for test (Fixed at “L”)
Input pin for test (Fixed at “L”)
Input pin for test (Fixed at “L”)
Ground (Digital)
EFM signal output for recording to overwrite head driver (IC181)
Pin Name
TFDR
DVDD
FFDR
FRDR
FS4
SRDR
SFDR
SPRD
SPFD
FGIN
TEST1
TEST2
TEST3
DVSS
EFMO
* I (S) of I/O is schmitt input, I (A) is analog input, O (3) is 3-state output, O (A) is analog output
66
Pin No.
1
2
3
4
5
6
7, 8
9
10
11
12
13
14
15, 16
17
18
19
20
21
22, 23
24, 25
26
27
28
29
30
31
32
33
34, 35
36
37
38
39
40
41
42
I/O
I
—
I
I
—
O
—
I
I
—
I
I
O
—
I
I
I
I
I
—
—
O
I
—
—
I
—
—
I
I
—
I
I
—
I
I
I
Description
Input pin for test (Fixed at “L”)
Not used in this system (Blank terminal)
Sync mode selector input. “L”: Slave mode. “H”: Master mode. Fixed to “L”
Reset signal input from the system controller (IC800) “L”: Reset
Not used in this system (Blank terminal)
Flag output terminal for calibration. Not used in this system (Blank terminal)
Power supply (+5 V)
L/R sampling clock signal input Not used (Fixed at “L”)
Bit clock signal input of serial input/output data. Not used in this system (Fixed at “L”)
Not used in this system (Blank terminal)
L channel data input (when 8Fs, 2Fs, and FS) Not used in this system (Fixed at “L”)
R channel data input (8FS and 2FS) FSYNC input when FS Not used in this system (Fixed at “L”)
Sync flag output terminal to the input side. Not used in this system (Blank terminal)
Not used in this system (Blank terminal)
FE selection IBIT (ed-pin) “L” LR selection when “H”
Fixed at “L” in this system
64FS data (L channel data) input Not used in this system (Fixed at “L”)
64FS data (R channel data) input Not used in this system (Fixed at “L”)
64FS data input from A/D converter (IC302) (L channel data)
64FS data input from A/D converter (IC302) (R channel data)
Ground
Ground (For oscillator circuit)
FE clock signal output to A/D converter (IC302) (128FS)
Master clock signal input to D/A converter (IC502) (256FS)
Power supply (+5 V) (For oscillator circuit)
Not used in this system (Blank terminal)
Input terminal to set the input data word length during 64 FS. “L: 1 bit, “H”: 4 bits. (Fixed at “L”)
Not used in this system (Blank terminal)
Ground
Input terminal to set the scaling amount during 64 FS. “L: x5, “H”: x4. (Fixed at “L”)
Input terminal to set the input sampling frequency. (Fixed both terminals to “L” = 64 FS)
Not used in this system (Blank terminal)
Input terminal to set the dizzer mode. “L: OFF, “H”: ON. (Fixed at “H”)
Input terminal to set the frequency compensation function. “L: OFF, “H”: ON. (Fixed at “H”)
Power supply terminal (+ 5V)
Mode data input Not used in this system (Fixed at “H”)
Serial data shift clock signal input Not used in this system (Fixed at “H”)
Serial data shift latch pulse input Not used in this system (Fixed at “H”)
Pin Name
TEST
NC
SYNC
INIT
NC
CLFG
VDD
LRKI
BKI
NC
DLI
DRI
IFLG
NC
LR
AL2
AR2
AL1
AR1
VSS
VSS
FCLK
MCLK
VDD
NC
IBIT
NC
VSS
SCALE
ISET1,ISET2
NC
DITH
BOOST
VDD
MODE
SHIFT
LATCH
• AD BOARD IC301 CXD8512Q (DIGITAL FILTER)
ISEL2
“H”
“L”
ISEL1
“H”
8FS
2FS
“L”
FS
64FS
67
Pin No.
43
44
45
46
47
48
49
50
51
52, 53
54
55
56
57
58
59
60
I/O
—
I
I
—
I
I
O
O
—
—
I
—
I
O
—
O
O
Description
Not used in this system (Blank terminal)
Input terminal to set the low-cut function. “L: OFF, “H”: ON. (Fixed at “H”)
Input terminal to set the noise shaving function. “L: OFF, “H”: ON. (Fixed at “H”)
Not used in this system. (Blank terminal)
Input pin for setting output sampling frequency
“L”: FS, “H”: 2FS (Fixed at “L” in this system)
Input terminal to set the output data word length. “L: 16 bit, “H”: 24 bits. (Fixed at “H”)
Data output during the 8FS and 2FS modes. WCK output during FS mode.
Not used in this system. (Blank terminal)
Recording data output to CXD2656R (IC121) of the MD mechanism deck
Not used in this system (Blank terminal)
Ground
Bit clock signal input (2.8224 MHz) from MD mechanism deck block CXD2656R (IC121)
Not used in this system (Blank terminal)
L/R sampling clock signal input (44.1 kHz) from MD mechanism deck block CXD2656R (IC121)
Sync flag output terminal of output side. Not used in this system (Blank terminal)
Power supply (+5 V)
Overflow flag output of R channel. Not used in this system (Blank terminal)
Overflow flag output of L channel. Not used in this system (Blank terminal)
Pin Name
NC
LC
NS
NC
OSEL
OBIT
DRO
DLO
NC
VSS
BCK
NC
LRCK
OFLG
VDD
OVR
OVL
68
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 to 30
31
32
33
34
35
36
37
38 to 47
48
49
50
51
52
53
I/O
I
I
O
O
I
I
I
I
—
I
O
I
O
—
I
—
I
I
I
I
I
I
O
O
O
I
O
O
O
I
O
O
I
I
I
I
I
O
Description
Jog dial pulse input from rotary encoder (S713 lAMSL) (phase B input)
Jog dial pulse input from rotary encoder (S713 lAMSL) (phase A input)
C1 error rate output during test mode (Blank terminal)
ADER output during test mode (Blank terminal)
Sub code Q sync (SCOR) input from CXD2656R (IC121) Input “L” every 13.3 msec “H” is input mostly
Remote control receiving signal input form remote control receiver (IC761)
SIRCS remote control signal input for the S-LINK control A1
Input terminal to select the external data bus width. “L: 16 bit, “H”: 8 bits. (Fixed at “L”)
Ground
Sub system clock input (32.768 kHz)
Sub system clock input (32.768 kHz)
System reset signal input from reset signal generator (IC240) “L”: Reset.
Input “L” during the several 100 ms after the power startup then change to the “H” input
Main system clock output (7 MHz)
Ground
Main system clock input (7 MHz)
Power supply (+3.3 V)
Non-maskable interrupt input terminal. Fixed at “H”)
Sub code Q sync (SCOR) input of digital-in U-bit CD format from CXD2656R (IC121)
Input “L” every 13.3 msec “H” is input mostly
Power down detection input. Input “L” when power down is detected
Interrupt status input from CXD2656R (IC121)
Jog dial pulse input from rotary encoder (S740 REC LEVEL DEGITAL) (phase B input)
Jog dial pulse input from rotary encoder (S740 REC LEVEL DEGITAL) (phase A input)
Reset signal output to A/D converter (IC302) “L”: Reset
Not used in this system (Blank terminal)
Write data output to CXD2656R (IC121) and CXD8762Q (IC501)
Read data input from CXD2656R (IC121)
Serial clock signal output to CXD2656R (IC121) and CXD8762Q (IC501)
Chip select signal output to fluorescent display tube/LED drive IC (IC771) “L”: Active
Serial data output for display to fluorescent display tube/LED drive IC (IC771)
Not used in this system (Fixed at “L”)
Serial data transfer clock signal output for display to fluorescent display tube/LED drive IC (IC771)
Not used in this system (Blank terminal)
Initial data input terminal for the watch setting in local time. Fixed to “H”
Initial data input terminal for the watch setting in local time. Fixed to “H”
Initial data input terminal for the loading control method. “H”: IN switch is not used. (Fixed at “H”)
Not used in this system (Fixed at “L”)
Busy monitor signal input from CXD2656R (IC121)
Reset signal output to CXD2656R (IC121), BH6511FS (IC152), CXD8512Q (IC301) “L”: Reset
Pin Name
JOG1
JOG0
C1ERO
ADERO
SQSY
RMC
A1IN
BYTE
CNVSS
XIN-T
XOUT-T
S.RST
XOUT
GND
XIN
+ 3.3 V
NMI
DQSY
P.DOWN
XINT
DVOL1
DVOL0
ADRST
NC
SWDT
SRDT
SCLK
FLCS
FLDATA
NC
FLCLK
NC
CSET0
CSET1
20/X720
NC
MNT2 (XBUSY)
DIG-RST
• AD BOARD IC800 M30624MG-215FP (SYSTEM CONTROLLER)
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